DSPB56725AF datasheet(16/48 Pages) FREESCALE

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Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

First SCK sampling edge to HREQ output

deassertion

Slave

Bypassed

—

Very Narrow

—

Narrow

—

Wide

—

145

—

Last SCK sampling edge to HREQ output

not deasserted (CPHA = 1)

Slave

Bypassed

—

50.0

—

Very Narrow

—

60.0

—

Narrow

—

100.0

—

Wide

—

150.0

—

SS deassertion to HREQ output not

deasserted (CPHA = 0)

Slave

—

45.0

—

SS deassertion pulse width (CPHA = 0)

Slave

—

TC + 6

11.0

—

HREQ in assertion to first SCK edge

Master

—

0.5

× TSPICC

+ 3.0

× TC + 43

96.0

—

HREQ in deassertion to last SCK sampling

edge (HREQ in set-up time) (CPHA = 1)

Master

—

First SCK edge to HREQ in not asserted

(HREQ in hold time)

Master

—

HREQ assertion width

Master

—

3.0

× TC

—

Note:

1. 0.95 V < VVDD_CORE < 1.05 V and TJ < 100° C, CL = 50 pF

2. Periodically sampled, not 100% tested

3. All times assume noise free inputs.

4. All times assume internal clock frequency of 200 MHz.

5. SHI_1 specs match those of SHI

6. Slave timings should equal the serial clock high period + the serial clock low period.

Table 9. Serial Host Interface SPI Protocol Timing (Continued)

No.

Characteristics1,3,4

Mode

Filter Mode

Expression

Min

Max

Unit

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