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DSPB56725AF Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc |
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DSPB56725AF Datasheet(HTML) 32 Page - Freescale Semiconductor, Inc |
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32 / 48 page ![]() Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 32 1.2.8 S/PDIF Timing Table 15 lists the S/PDIF timing. Figure 25 shows the SRCK timing diagram. Figure 25. SRCK Timing Figure 26 shows the STCLK timing diagram. Figure 26. STCLK Timing Table 15. S/PDIF Timing Characteristics Symbol All Frequency Unit Min Max SPDIFIN1, SPDIFIN2, SPDIFIN3, SPDIFIN4 Skew: asynchronous inputs, no specs apply —— 0.7 ns SPDIFOUT1,SPDIFOUT2 output (Load = 50pf) •Skew • Transition Rising • Transition Falling — — — — — — 1.5 24.2 31.3 ns SPDIFOUT1, SPDIFOUT2 output (Load = 30pf) •Skew • Transition Rising • Transition Falling — — — — — — 1.5 13.6 18.0 ns SRCK period srckp 40.0 — ns SRCK high period srckph 16.0 — ns SRCK low period srckpl 16.0 — ns STCLK period stclkp 40.0 — ns STCLK high period stclkph 16.0 — ns STCLK low period stclkpl 16.0 — ns SRCK (Output) VM VM srckp srckph srckpl STCLK (Input) VM VM stclkp stclkph stclkpl |
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