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DSPB56725AF Datasheet(PDF) 28 Page - Freescale Semiconductor, Inc |
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DSPB56725AF Datasheet(HTML) 28 Page - Freescale Semiconductor, Inc |
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28 / 48 page ![]() Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 28 Figure 20 shows the ESAI HCKR timing diagram. Figure 20. ESAI HCKR Timing 1.2.5 GPIO Timing Table 12 lists the GPIO timing. Table 12. GPIO Timing No. Characteristics1 Expression Min Max Unit 100 Fsys edge to GPIO out valid (GPIO out delay time)2 —— 7 ns 101 Fsys edge to GPIO out not valid (GPIO out hold time)2 —— 7 ns 102 Fsys In valid to EXTAL edge (GPIO in set-up time)2 —2 — ns 103 Fsys edge to GPIO in not valid (GPIO in hold time)2 —0 — ns 104 Minimum GPIO pulse high width 2 × TC 10 — ns 105 Minimum GPIO pulse low width 2 × TC 10 — ns 106 GPIO out rise time — — 13.0 ns 107 GPIO out fall time — — 13.0 ns Note: 1. 0.95 V < VVDD_CORE < 1.05 V and Tj < 100° C, CL = 50 pF 2. Simulation numbers-subject to change. HCKR SCKR (output) 97 95 |
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