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DSPB56725AF Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc |
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DSPB56725AF Datasheet(HTML) 36 Page - Freescale Semiconductor, Inc |
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36 / 48 page  Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1 Freescale Semiconductor 36 Figure 28 shows the EMC signals diagram, with EMC PLL bypassed. Figure 28. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4 Table 18 lists the EMC timing parameters with EMC PLL bypassed. Table 18. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) Parameter Symbol Min Max Unit LCLK cycle time Tclk 8 × Tc —ns Input setup to LCLK (except LGTA/LUPWAIT) Tin_s 8— ns Input hold from LCLK (except LGTA/LUPWAIT)1 Tin_h –1 — ns LGTA valid time Tgta 42 — ns LUPWAIT valid time Tupwait 42 — ns LALE negedge to LAD (address phase) invalid (address latch hold time) Tale_h 5— ns LALE valid time Tale 34 — ns Tin_s Tin_h LGTA asynchronous input LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LGPL[5:0] Output Signals LCLK LAD[23:0] (data) Tclk LUPWAIT asynchronous input Tgta Tupwait Tout_s Tout_h LALE Tad_s Tad_h LAD[23:0] Tad_z LSDWE/LSDRAS/LSDCAS Tale Tale_h |
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