ACS8525AP datasheet(43/112 Pages) SEMTECH

43 / 112 page

ACS8525A LC/P

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Revision 1.00/September 2007 © Semtech Corp.

Page 43

www.semtech.com

Address (hex):

Description

(R/W) Register containing various

test controls (not normally used).

Default Value

0001 0100

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

phase_alarm

disable_180

resync_analog

Set to 0

8k Edge Polarity Set to 0

Set to 0

Bit No.

Description

Bit Value

Value Description

phase_alarm (phase alarm (R/O))

Instantaneous result from DPLL1.

DPLL1 reporting phase locked.

DPLL1 reporting phase lost.

disable_180

Normally the DPLL will try to lock to the nearest

edge (±180

°) for the first 2 seconds when locking to

a new reference. If the DPLL does not determine

that it is phase locked after this time, then the

capture range reverts to ±360

°, which corresponds

to frequency and phase locking. Forcing the DPLL

into frequency locking mode may reduce the time to

frequency lock to a new reference by up to two

seconds. However, this may cause an unnecessary

phase shift of up to 360

° when the new and old

references are very close in frequency and phase.

DPLL1 automatically determines frequency lock

enable.

DPLL1 forced to always frequency and phase lock.

5Not used.

resync_analog (analog dividers re-synchronization)

The analog output dividers include a

synchronization mechanism to ensure phase lock at

low frequencies between the input and the output.

Analog divider only synchronized during first 2

seconds after power-up.

Analog dividers always synchronized.This keeps the

clocks divided down from the APLL output, in sync

with equivalent frequency digital clocks in the DPLL.

Hence ensuring that 6.48 MHz output clocks, and

above, are in sync with the DPLL even though only a

77.76 MHz clock drives the APLL.

Set to 0

Test Control. Leave unchanged or set to 0.

8k Edge Polarity

When lock 8k mode is selected for the current input

SEC, this bit allows the system to lock on either the

rising or the falling edge of the input clock.

Lock to falling clock edge.

Lock to rising clock edge.

Set to 0

Test Control. Leave unchanged or set to 0.

Set to 0

Test Control. Leave unchanged or set to 0.

Address (hex):

test_register2

Do not use. Only zero should be written to this address.

ACS8525AP Datasheet(PDF) 43 Page - Semtech Corporation

ACS8525AP Datasheet(HTML) 43 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL