Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

ACS8525AP Datasheet(PDF) 85 Page - Semtech Corporation

Part # ACS8525AP
Description  Line Card Protection Switch for SONET/SDH Systems
PDF  112 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

ACS8525AP Datasheet(HTML) 85 Page - Semtech Corporation

Back Button ACS8525AP Datasheet HTML 81Page - Semtech Corporation ACS8525AP Datasheet HTML 82Page - Semtech Corporation ACS8525AP Datasheet HTML 83Page - Semtech Corporation ACS8525AP Datasheet HTML 84Page - Semtech Corporation ACS8525AP Datasheet HTML 85Page - Semtech Corporation ACS8525AP Datasheet HTML 86Page - Semtech Corporation ACS8525AP Datasheet HTML 87Page - Semtech Corporation ACS8525AP Datasheet HTML 88Page - Semtech Corporation ACS8525AP Datasheet HTML 89Page - Semtech Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 85 / 112 page
background image
ACS8525A LC/P
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 © Semtech Corp.
Page 85
www.semtech.com
[2:0]
DPLL2_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking to a reference in digital feedback
mode. This setting is always used if automatic gain
selection is disabled in Bit 7,
DPLL2_PD2_gain_enable.
-
Gain value of Phase Detector 2 when locking to any
reference in digital feedback mode.
Address (hex):
6D
Register Name cnfg_DPLL1_PD2_gain
Description
(R/W) Register to configure the
gain of Phase Detector 2 in some
modes for DPLL1.
Default Value
1100 0010
Bit 7Bit 6
Bit 5Bit 4
Bit 3
Bit 2Bit 1Bit 0
DPLL1_PD2_
gain_enable
DPLL1_PD2_gain_alog
DPLL1_PD2_gain_digital
Bit No.
Description
Bit Value
Value Description
7
DPLL1_PD2_gain_enable
0
1
DPLL2 Phase Detector 2 not used.
DPLL2 Phase Detector 2 gain enabled and choice of
gain determined according to the locking mode:
- digital feedback mode
- analog feedback mode
- analog feedback at 8 kHz
[6:4]
DPLL1_PD2_gain_alog
Register to control the gain of Phase Detector 2
when locking to a reference, higher than 8 kHz, in
analog feedback mode. This setting is not used if
automatic gain selection is disabled in Bit 7,
DPLL1_PD2_gain_enable.
-
Gain value of Phase Detector 2 when locking to a
high frequency reference in analog feedback mode.
3Not used.
-
-
Address (hex):
6C (cont...)
Register Name cnfg_DPLL2_PD2_gain
Description
(R/W) Register to configure the
gain of Phase Detector 2 in some
modes for DPLL2.
Default Value
1100 0010
Bit 7Bit 6
Bit 5Bit 4
Bit 3
Bit 2Bit 1Bit 0
DPLL2_PD2_
gain_enable
DPLL2_PD2_gain_alog
DPLL2_PD2_gain_digital
Bit No.
Description
Bit Value
Value Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com