ACS8525AP datasheet(68/112 Pages) SEMTECH

68 / 112 page

ACS8525A LC/P

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Revision 1.00/September 2007 © Semtech Corp.

Page 68

www.semtech.com

Address (hex):

Description

(R/W) Register to select the

source of many of the registers.

Default Value

0000 0000

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

DPLL1_DPLL2_

select

Bit No.

Description

Bit Value

Value Description

[7:5]

Not used.

DPLL1_DPLL2_select

Bit to select between many of the registers

associated with DPLL1 or DPLL2 e.g. frequency

registers.

DPLL1 registers selected.

DPLL2 registers selected.

[3:0]

Not used.

Address (hex):

Description

(R/W) Register to enable the

phase lost indication when DPLL

hits its hard frequency limit.

Default Value

1000 1110

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

freq_lim_ph_

loss

Bit No.

Description

Bit Value

Value Description

freq_lim_ph_loss

Bit to enable the phase lost indication when the

DPLL hits its hard frequency limit as programmed in

Reg. 41 and Reg. 42 (cnfg_DPLL_freq_limit). This

results in the DPLL entering the phase lost state any

time the DPLL tracks to the extent of its hard limit.

Phase lost/locked determined normally.

Phase lost forced when DPLL tracks to hard limit.

[6:0]

Not used.

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