ACS8525AP datasheet(32/112 Pages) SEMTECH

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ACS8525A LC/P

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Revision 1.00/September 2007 © Semtech Corp.

Page 32

www.semtech.com

Pre-locked2 Mode

This state is very similar to the Pre-locked state. It is

entered from the Digital Holdover state when an input

SEC has been selected and applied to the phase locked

loop. It is also entered if the device is operating in

Revertive mode and a higher-priority SEC is restored.

Upon applying a SEC to the phase locked loop, the

ACS8525A will enter the Locked state in a maximum of

100 seconds, as defined by GR-1244-CORE[13]

specification, if the selected SEC is of good quality. If the

device cannot achieve lock within 100 seconds, it reverts

to Digital Holdover mode and another SEC is selected.

Local Oscillator Clock

The Master system clock on the ACS8525A should be

provided by an external clock oscillator of frequency

12.800 MHz. Wander on the local oscillator clock will not

have a significant effect on the output clock whilst in

Locked mode. In Free-Run or Holdover mode wander on

the crystal is more significant. Variation in crystal

temperature or supply voltage both cause drifts in

operating frequency, as does ageing. These effects must

be limited by careful selection of a suitable component for

the local oscillator. Please contact Semtech for

information on crystal oscillator suppliers.

Crystal Frequency Calibration

The absolute crystal frequency accuracy is less important

than the stability since any frequency offset can be

compensated by adjustment of register values in the IC.

This allows for calibration and compensation of any

crystal frequency variation away from its nominal value.

± 50 ppm adjustment would be sufficient to cope with

most crystals, in fact the range is an order of magnitude

larger due to the use of two 8-bit register locations. The

setting of the cnfg_nominal_frequency register allows for

this adjustment. An increase in the register value

increases the output frequencies by 0.0196229 ppm for

each LSB step.

Note...The default register value (in decimal) = 39321

(9999 hex) = 0 ppm offset. The minimum to maximum offset

range of the register is 0 to 65535 (dec), giving an adjustment

range of -771 ppm to +514 ppm of the output frequencies, in

0.0196229 ppm steps.

Example: If the crystal was oscillating at 12.800 MHz + 5 ppm,

then the calibration value in the register to give a - 5 ppm

adjustment in output frequencies to compensate for the

crystal inaccuracy, would be:

39321 - (5 / 0.0196229) = 39066 (dec) = 989A (hex).

Status Reporting and Phase Measurement

Input Status Interrupts

Status interrupts are provided for the following events:

Changed status on SEC input (one interrupt per input)

(Reg. 05)

Change of Operating mode (Reg. 06)

DPLL1 Main reference Failure (Reg. 06)

Frame Sync alarm limit reached (Reg. 08)

These interrupts are flagged on pin INTREQ.

Input Status Information

Status information can be read from the following Status

Registers:

sts_operating_mode (Reg. 09)

sts_priority_table (Reg. 0A and 0B)

sts_current_DPLL_frequency (Reg. 0C, 0D, and 07)

sts_sources_valid (Reg. 0E and 0F)

sts_reference_sources (Reg. 11, 12 and 14)

Refer to “Register Map” on page 38 and associated

DPLL Frequency Reporting

The registers sts_current_DPLL_frequency (Reg. 0C, 0D

and 07) report the frequency of DPLL1 or DPLL2 with

respect to the external crystal XO frequency (after

calibration via Reg. 3C, 3D if used). The selection of

DPLL2 or DPLL1 reporting is made via Reg. 4B, Bit 4. The

value is a 19-bit signed number with one LSB

representing 0.0003068 ppm (range of ±80 ppm). This

value is actually the integral path value in the DPLL, and

as such corresponds to an averaged measurement of the

input frequency, with an averaging time inversely

proportional to the DPLL bandwidth setting. Reading this

regularly can show how the currently locked source is

varying in value e.g. due to frequency wander on its input.

The input phase, as seen at the DPLL phase detector, can

be read back from register sts_current_phase, Reg. 77

and 78. DPLL1 or DPLL2 phase detector reporting is

again controlled by Reg. 4B, Bit 4. One LSB corresponds

to 0.707° phase difference. For DPLL1 this will be

reporting the phase difference between the input and the

internal feedback clock. The phase result is internally

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