ACS8525AP datasheet(95/112 Pages) SEMTECH

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ACS8525A LC/P

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Revision 1.00/September 2007 © Semtech Corp.

Page 95

www.semtech.com

6Sync_OC-N_rates

This allows the selected Sync input to synchronize

the OC-3 derived clocks in order to maintain

alignment between the FrSync output and output

clocks and allow a finer sampling precision of the

selected Sync input of either 19.44MHz or

38.88MHz.

The OC-N rate clocks are not affected by the

selected Sync input. The selected Sync input is

sampled with a 6.48 MHz precision. 6.48MHz

should be provided as the input reference clock.

Allows the selected Sync input to operate with a

19.44 MHz or 38.88 MHz input clock reference.

Input sampling and output alignment to 19.44 MHz

is used when the current clock input is 19.44 MHz,

otherwise 38.88 MHz sampling precision is used.

[5:4]

Sync_phase_SYNC3

input. Nominally the falling edge of the input is

aligned with the falling edge of the reference clock.

The margin is ±0.5 U.I. (Unit Interval).

On target.

0.5 U.I. early.

1 U.I. late.

0.5 U.I. late.

[3:2]

Sync_phase_SYNC2

input. Nominally the falling edge of the input is

aligned with the falling edge of the reference clock.

The margin is ±0.5 U.I. (Unit Interval).

On target.

0.5 U.I. early.

1 U.I. late.

0.5 U.I. late.

[1:0]

Sync_phase_SYNC1

input. Nominally the falling edge of the input is

aligned with the falling edge of the reference clock.

The margin is ±0.5 U.I. (Unit Interval).

On target.

0.5 U.I. early.

1 U.I. late.

0.5 U.I. late.

Address (hex):

7B (cont...)

Description

(R/W) Register to configure the

behaviour of the synchronisation

for the external frame reference.

Default Value

0000 0000

Bit 7Bit 6

Bit 5Bit 4

Bit 3

Bit 2Bit 1Bit 0

Indep_FrSync/

MFrSync

Sync_OC-N_

rates

Sync_phase_SYNC3

Sync_phase_SYNC2

Sync_phase_SYNC1

Bit No.

Description

Bit Value

Value Description

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