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ACS8525AP Datasheet(PDF) 93 Page - Semtech Corporation |
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ACS8525AP Datasheet(HTML) 93 Page - Semtech Corporation |
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93 / 112 page  ACS8525A LC/P ADVANCED COMMS & SENSING FINAL DATASHEET Revision 1.00/September 2007 © Semtech Corp. Page 93 www.semtech.com [5:0] timeout_value Phase alarms can only be raised on an input when DPLL1 is attempting to lock to it. Once an input has been rejected due to a phase alarm, there is no way to measure whether it is good again, because it is no longer selected by the DPLL. The phase alarms can either remain until reset by software, or timeout after 128 seconds, as selected in Reg. 34 Bit 6, phalarm_timeout. - This 6-bit unsigned integer represents the length of time before a phase alarm will be raised on an input. The value multiplied by 2 gives the time in seconds. This time value is the time that the controlling state machine will spend in Pre-locked, Pre-locked2 or Phase-lost modes before setting the phase alarm on the selected input. Address (hex): 7A Register Name cnfg_sync_pulses Description (R/W) Register to configure the Sync outputs available from FrSync and MFrSync and select the source for the 2 kHz and 8 kHz outputs from O1 and O2. Default Value 0000 0000 Bit 7Bit 6 Bit 5Bit 4 Bit 3 Bit 2Bit 1Bit 0 2k_8k_from_ DPLL2 8k_invert 8k_pulse 2k_invert 2k_pulse Bit No. Description Bit Value Value Description 7 2k_8k_from_DPLL2 Register to select the source (DPLL1 or DPLL2) for the 2 kHz and 8 kHz outputs available from O1 and O2. 0 1 2/8 kHz on O1 and O2 generated from DPLL1. 2/8 kHz on O1 and O2 generated from DPLL2. [6:4] Not used. - - 3 8k_invert Register bit to invert the 8 kHz output from FrSync. 0 1 8 kHz FrSync output not inverted. 8 kHz FrSync output inverted. 2 8k_pulse Register bit to enable the 8 kHz output from FrSync to be either pulsed or 50:50 duty cycle. Output 02 must be enabled to use “pulsed output” mode on the FrSync output, and then the pulse width on the FrSync output will be equal to the period of the output programmed on O2. 0 1 8 kHz FrSync output not pulsed. 8 kHz FrSync output pulsed. Address (hex): 79 (cont...) Register Name cnfg_phase_alarm_timeout Description (R/W) Register to configure how long before a phase alarm is raised on an input. Default Value 0011 0010 Bit 7Bit 6 Bit 5Bit 4 Bit 3 Bit 2Bit 1Bit 0 timeout_value (in two-second intervals) Bit No. Description Bit Value Value Description |
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