SC28L92 datasheet(32/73 Pages) NXP

32 / 73 page

SC28L92_7

Product data sheet

Rev. 07 — 19 December 2007

32 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

[1]

Add 0.5 to values shown for 0 to 7 if channel is programmed for 5 bit per character

7.3.1.4

Mode Register 0 channel B (MR0B)

MR0B (address 0x8) is accessed when the channel B MR pointer points to MR1. The

pointer is set to MR0 by RESET or by a set pointer command applied via CRB. After

reading or writing MR0B, the pointer will point to MR1B.

The bit deﬁnitions for this register are identical to MR0A, except the FIFO size bit and that

all control actions apply to the channel B receiver, transmitter, the corresponding inputs

and outputs. MR0B[2:0] are reserved.

7.3.1.5

Mode Register 1 channel B (MR1B)

MR1B (address 0x8) is accessed when the channel B MR pointer points to MR1. The

pointer is set to MR1 by RESET or by a set pointer command applied via CRB. After

reading or writing MR1B, the pointer will point to MR2B.

The bit deﬁnitions for this register are identical to MR1A, except that all control actions

apply to the channel B receiver and transmitter and the corresponding inputs and outputs.

7.3.1.6

Mode Register 2 channel B (MR2B)

MR2B (address 0x8) is accessed when the channel B MR pointer points to MR2, which

occurs after any access to MR1B. Accesses to MR2B do not change the pointer.

The bit deﬁnitions for mode register are identical to the bit deﬁnitions for MR2A, except

that all control actions apply to the channel B receiver and transmitter and the

corresponding inputs and outputs.

1.750

1.813

1.875

1.938

2.000

Table 32.

Stop bit length …continued

MR2A[3:0] (hexadecimal)

Stop bit length[1]

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