SC28L92 datasheet(38/73 Pages) NXP

38 / 73 page

SC28L92_7

Product data sheet

Rev. 07 — 19 December 2007

38 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

Channel A overrun error.

0 = no

1 = yes

This bit, when set, indicates that one or more characters in the received data

stream have been lost. It is set upon receipt of a new character when the FIFO

is full and a character is already in the receive shift register waiting for an empty

FIFO position. When this occurs, the character in the receive shift register (and

its break detect, parity error and framing error status, if any) is lost.

This bit is cleared by a reset error status command.

TxEMTA

Channel A transmitter empty.

0 = no

1 = yes

This bit will be set when the transmitter under runs, i.e., both the TxEMT and

TxRDY bits are set. This bit and TxRDY are set when the transmitter is ﬁrst

enabled and at any time it is re-enabled after either (a) reset, or (b) the

transmitter has assumed the disabled state. It is always set after transmission

of the last stop bit of a character if no character is in the Tx Holding Register

(TxFIFOA) awaiting transmission.

It is reset when the Tx Holding Register (TxFIFOA) is loaded by the CPU, a

pending transmitter disable is executed, the transmitter is reset, or the

transmitter is disabled while in the under run condition.

TxRDYA

Channel A transmitter ready.

0 = no

1 = yes

This bit, when set, indicates that the transmit FIFO is not full and ready to be

loaded with another character. This bit is cleared when the transmit FIFO is

loaded by the CPU and there are (after this load) no more empty locations in

the FIFO. It is set when a character is transferred to the transmit shift register.

TxRDYA is reset when the transmitter is disabled and is set when the

transmitter is ﬁrst enabled. Characters loaded to the Tx FIFO while this bit is

logic 0 will be lost. This bit has different meaning from ISR[0].

FFULLA

Channel A FIFO full.

0 = no

1 = yes

This bit is set when a character is transferred from the receive shift register to

the receive FIFO and the transfer causes the FIFO to become full, i.e., all eight

(or 16) FIFO positions are occupied. It is reset when the CPU reads the receive

FIFO. If a character is waiting in the receive shift register because the FIFO is

full, FFULLA will not be reset when the CPU reads the receive FIFO. This bit

has different meaning from ISR1 when MR1[6] is programmed to a logic 1

RxRDYA

Channel A receiver ready.

0 = no

1 = yes

This bit indicates that a character has been received and is waiting in the FIFO

to be read by the CPU. It is set when the character is transferred from the

receive shift register to the FIFO and reset when the CPU reads the receive

FIFO, only if (after this read) there are no more characters in the FIFO - the Rx

FIFO becomes empty.

Table 42.

SRA - Status register channel A (address 0x1) bit description …continued

Bit

Symbol

Description

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