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SC28L92 Datasheet(PDF) 59 Page - NXP Semiconductors |
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SC28L92 Datasheet(HTML) 59 Page - NXP Semiconductors |
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59 / 73 page  SC28L92_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 19 December 2007 59 of 73 NXP Semiconductors SC28L92 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter DACKN LOW requires two rising edges of X1 clock after CEN is LOW. Fig 12. Bus timing, read cycle (68xxx mode) DACKN LOW requires two rising edges of X1 clock after CEN is LOW. Fig 13. Bus timing, write cycle (68xxx mode) A0 to A3 tCSC tCS tAS tRWD D0 to D7 tDD tDF 001aae306 X1/CLK R/WN CEN tCH tAH not valid data valid DACKN tDA tDCR tDAT tDAH A0 to A3 tCSC tCS tAS tRWD D0 to D7 X1/CLK R/WN CEN tCH tAH DACKN tDH tDS 001aae308 tDCW tDAT tDAH |
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