SC28L92 datasheet(12/73 Pages) NXP

12 / 73 page

SC28L92_7

Product data sheet

Rev. 07 — 19 December 2007

12 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

INTRN

Interrupt request: Active LOW, open-drain, output which signals the

CPU that one or more of the eight maskable interrupting conditions

are true. This pin requires a pull-up.

X1/CLK

Crystal 1: Crystal or external clock input. A crystal or clock of the

speciﬁed limits must be supplied at all times. When a crystal is used, a

capacitor must be connected from this pin to ground (see Figure 17).

Crystal 2: Connection for other side of the crystal. When a crystal is

used, a capacitor must be connected from this pin to ground (see

Figure 17). If X1/CLK is driven from an external source, this pin must

be left open.

RxDA

Channel A receiver serial data input: The least signiﬁcant bit is

received ﬁrst. See note on drive levels at block diagram (Figure 2).

RxDB

Channel B receiver serial data input: The least signiﬁcant bit is

received ﬁrst. See note on drive levels at block diagram (Figure 2).

TxDA

Channel A transmitter serial data output: The least signiﬁcant bit is

transmitted ﬁrst. This output is held in the ‘mark condition when the

transmitter is disabled, idle or when operating in local loopback mode.

See note on drive levels at block diagram (Figure 2).

TxDB

Channel B transmitter serial data output: The least signiﬁcant bit is

transmitted ﬁrst. This output is held in the Mark condition when the

transmitter is disabled, idle, or when operating in local loopback mode.

See note on drive levels at block diagram (Figure 2).

OP0

Output 0: General purpose output or channel A request to send

(RTSAN, active LOW). Can be deactivated automatically on receive or

transmit.

OP1

Output 1: General purpose output or channel B request to send

(RTSBN, active LOW). Can be deactivated automatically on receive or

transmit.

OP2

Output 2: General purpose output, or channel A transmitter 1

× or 16×

clock output, or channel A receiver 1

× clock output.

OP3

Output 3: General purpose output or open-drain, active LOW

counter/timer output or channel B transmitter 1

× clock output, or

channel B receiver 1

× clock output.

OP4

Output 4: General purpose output or channel A open-drain, active

LOW, RxA interrupt ISR [1] output.

OP5

Output 5: General purpose output or channel B open-drain, active

LOW, RxB interrupt ISR[5] output.

OP6

Output 6: General purpose output or channel A open-drain, active

LOW, TxA interrupt ISR[0] output.

OP7

Output 7: General purpose output, or channel B open-drain, active

LOW, TxB interrupt ISR[4] output.

IP0

Input 0: General purpose input or channel A clear to send active LOW

input (CTSAN).

IP1

Input 1: General purpose input or channel B clear to send active LOW

input (CTSBN).

IP2

Input 2: General purpose input or counter/timer external clock input.

Table 3.

Pin description for 68xxx bus interface (Motorola) …continued

Symbol

Type

Description

PLCC44

QFP44

HVQFN48

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