SC28L92 datasheet(55/73 Pages) NXP

55 / 73 page

SC28L92_7

Product data sheet

Rev. 07 — 19 December 2007

55 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

[1]

The following conditions apply:

a) Parameters are valid over speciﬁed temperature and voltage range.

b) All voltage measurements are referenced to ground. For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of

5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8VCC. All time measurements are referenced at input voltages of 0.8 V

and 2.0 V, and output voltages of 0.8 V and 2.0 V, as appropriate.

c) Test conditions for outputs: CL = 125 pF, except open-drain outputs. Test conditions for open-drain outputs: CL = 125 pF,

constant current source = 2.6 mA.

d) Typical values are the average values at +25

°C and 5 V.

[2]

Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the strobing input. CEN and RDN (also CEN and

WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated ﬁrst terminates the cycle.

[3]

Guaranteed by characterization of sample units.

[4]

If CEN is used as the strobing input, the parameter deﬁnes the minimum HIGH times between one CEN and the next. The RDN signal

must be negated for tRWD to guarantee that any status register changes are valid.

[5]

Minimum frequencies are not tested but are guaranteed by design.

[6]

Clocks for 1

× mode should maintain a 60/40 duty cycle or better.

Clock timing (see Figure 17)

tCLK

X1/CLK HIGH or LOW time

fCLK

X1/CLK frequency

[5] 0.1

3.686

MHz

tCTC

C/T clock (IP2) HIGH or LOW time (C/T

external clock input)

fCTC

C/T clock (IP2) frequency

[5] 0-

8MHz

tRX

RxC HIGH or LOW time

fRX

RxC frequency

MHz

[5][6] 0-

1MHz

tTX

TxC HIGH or LOW time

fTX

TxC frequency

--16

MHz

[5][6] 0-

1MHz

Transmitter timing, external clock (see Figure 18)

tTXD

TxD output delay from TxC LOW (TxC

input pin)

4060ns

tTCS

output delay from TxC output pin LOW to

TxD data output

Receiver timing, external clock (see Figure 19)

tRXS

RxD data set-up time to RxC HIGH

tRXH

RxD data hold time from RxC HIGH

68xxx or Motorola bus timing (see Figure 12, 13 and 14)[7]

tDCR

DACKN LOW (read cycle) from X1 HIGH

[7] -

1535ns

tDCW

DACKN LOW (write cycle) from X1 HIGH

tDAT

DACKN high-impedance from CEN or

IACKN HIGH

tCSC

CEN or IACKN set-up time to X1 HIGH for

minimum DACKN cycle

Table 67.

Dynamic characteristics, 5 V operation[1] …continued

VCC = 5.0 V ± 10 %, Tamb = −40 °C to +85 °C, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SC28L92 Datasheet(PDF) 55 Page - NXP Semiconductors

SC28L92 Datasheet(HTML) 55 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL