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SC28L92 Datasheet(PDF) 63 Page - NXP Semiconductors |
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SC28L92 Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 73 page ![]() SC28L92_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 19 December 2007 63 of 73 NXP Semiconductors SC28L92 3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter (1) Timing shown for MR2[4] = 1. (2) Timing shown for MR2[5] = 1. Fig 20. Transmitter timing D1 D2 D3 D4 D6 D1 D8 D9 D10 D12 OPR(0) = 1 OPR(0) = 1 001aae317 D11 will not be written to the TxFIFO RTSN(2) (OP0) CTSN(1) (IP0) start break stop break WRN TxRDY (SR2) transmitter enabled TxD break (1) Timing shown for MR1[7] = 1. (2) Shown for OPCR[4] = 1 and MR[6] = 0. Fig 21. Receiver timing D1 D2 D8 D9 D10 D11 D12 D13 RDN D1 D2 D3 D10 OPR[0] = 1 001aae318 RTS(1) (OP0) OVERRUN (SR) reset by command status data status data D11 will be lost due to overrun status data status data RxRDY/ FFULL (OP5)(2) FFULL (CR) RxRDY (SR) receiver enabled D12, D13 will be lost due to receiver disable RxD |
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