SC28L92 datasheet(11/73 Pages) NXP

11 / 73 page

SC28L92_7

Product data sheet

Rev. 07 — 19 December 2007

11 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

[1]

HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

GND

16, 17

18[1]

Pwr

Ground

n.c.

1, 23, 34 23

6, 13, 24, 25,

36, 37, 43

Pwr

Not connected

Table 2.

Pin description for 80xxx bus interface (Intel) …continued

Symbol

Type

Description

PLCC44 QFP44

HVQFN48

Table 3.

Pin description for 68xxx bus interface (Motorola)

Symbol

Type

Description

PLCC44

QFP44

HVQFN48

I/M

Bus conﬁguration: When LOW conﬁgures the bus interface to the

conditions shown in this table.

I/O

Data bus: Bidirectional 3-state data bus used to transfer commands,

data and status between the DUART and the CPU. D0 is the least

signiﬁcant bit.

I/O

CEN

Chip enable: Active LOW input signal. When LOW, data transfers

between the CPU and the DUART are enabled on D0 to D7 as

controlled by the R/WN and A0 to A3 inputs. When HIGH, places the

D0 to D7 lines in the 3-state condition.

R/WN

Read/Write: Input signal. When CEN is LOW, R/WN HIGH input

indicates a read cycle; when LOW indicates a write cycle.

IACKN

Interrupt acknowledge: Active LOW input indicating an interrupt

acknowledge cycle. Usually asserted by the CPU in response to an

interrupt request. When asserted places the interrupt vector on the

bus and asserts DACKN.

DACKN

Data transfer acknowledge: A3-state active LOW output asserted in

a write, read, or interrupt acknowledge cycle to indicate proper

transfer of data between the CPU and the DUART.

Address inputs: Select the DUART internal registers and ports for

read/write operations.

RESETN 38

Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR,

OPR, OPCR), puts OP0 to OP7 in the HIGH state, stops the

counter/timer, and puts channels A and B in the inactive state, with the

TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to

MR1. See Figure 10.

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