SC28L92 datasheet(9/73 Pages) NXP

9 / 73 page

SC28L92_7

Product data sheet

Rev. 07 — 19 December 2007

9 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

5.2 Pin description

Table 2.

Pin description for 80xxx bus interface (Intel)

Symbol

Type

Description

PLCC44 QFP44

HVQFN48

I/M

Bus conﬁguration: When HIGH or not connected conﬁgures the bus

interface to the conditions shown in this table.

I/O

Data bus: Bidirectional 3-state data bus used to transfer commands,

data and status between the DUART and the CPU. D0 is the least

signiﬁcant bit.

I/O

CEN

Chip enable: Active LOW input signal. When LOW, data transfers

between the CPU and the DUART are enabled on D0 to D7 as

controlled by the WRN, RDN and A0 to A3 inputs. When HIGH, places

the D0 to D7 lines in the 3-state condition.

WRN

Write strobe: When LOW and CEN is also LOW, the contents of the

data bus is loaded into the addressed register. The transfer occurs on

the rising edge of the signal.

RDN

Read strobe: When LOW and CEN is also LOW, causes the contents

of the addressed register to be presented on the data bus. The read

cycle begins on the falling edge of RDN.

Address inputs: Select the DUART internal registers and ports for

read/write operations.

RESET

Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR,

OPR and OPCR), puts OP0 to OP7 in the HIGH state, stops the

counter/timer, and puts channels A and B in the inactive state, with the

TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to

MR1. See Figure 10.

INTRN

Interrupt request: Active LOW, open-drain, output which signals the

CPU that one or more of the eight maskable interrupting conditions are

true. This pin requires a pull-up device.

X1/CLK

Crystal 1: Crystal or external clock input. A crystal or clock of the

speciﬁed limits must be supplied at all times. When a crystal is used, a

capacitor must be connected from this pin to ground (see Figure 17).

Crystal 2: Connection for other side of the crystal. When a crystal is

used, a capacitor must be connected from this pin to ground (see

Figure 17). If X1/CLK is driven from an external source, this pin must

be left open.

RxDA

Channel A receiver serial data input: The least signiﬁcant bit is

received ﬁrst. See note on drive levels at block diagram (Figure 1).

RxDB

Channel B receiver serial data input: The least signiﬁcant bit is

received ﬁrst. See note on drive levels at block diagram (Figure 1).

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