CDCE906 datasheet(35/42 Pages) TI

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CDCE906Cyrstal27MHzInput

27MHzBufferedOutput

CDCE906fOUT 135MHz

135MHz

VCO

foffset -[Hz]

CDCE906fOUT 135MHz

270MHz

VCO

PhaseNoiseComparison

135MHz

135MHzvs270MHz

OUT

VCO

PLL Lock-Time

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

Figure 33. Phase Noise Characteristic

Some applications use frequency switching, i.e. to change frequency in TV application (switching between

channels) or change the PCI-X frequency in computers. The time spent by the PLL in achieving the new

frequency is of main interest. The lock time is the time it takes to jump from one specified frequency to another

specified frequency within a given frequency tolerance (Figure 34). It should be low, because a long lock time

impacts the data rate of the system.

The PLL Lock Time depends on the device configuration and can be changed by the VCO frequency, i.e. by

changing the M/N divider values. Table 7 gives the typical lock times of the CDCE906 and Figure 34 shows a

snapshot of a frequency switch.

Table 7. CDCE906 PLL Lock-Times

Description

Lock Time (Typical)

Unit

Frequency change via reprogramming of N/M counter

100

µs

Frequency change via CLK_SEL pin (switching between CLK_IN0 and CLK_IN1)

100

µs

Power-up lock time with system clock

µs

Power-up lock time with 27-MHz Crystal at CLK_IN0 and CLK_IN1

300(1)

µs

(1)

Is the result of crystal power up (200

µs) and PLL Lock Time (100 µs).

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