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PLL1

XO

or

2LVCMOS

or

Differential

Input

MUX

MUX

DividerM

1

MUX

DividerM

375

PLL3

PFD

Filter

VCO

PLL2

w/SSC

PFD

Filter

VCO

DividerN

8

DividerN

250

DividerN

3136

SO/CLK_SEL

S1

SCLOCK

OutputSwitchMatrix

27MHz

PROGRAMMING

LOGIC

SMBUS

LOGIC

PFD

Filter

VCO

SDATA

P0-Div

10

P1-Div

20

P2-Div

8

P3-Div

9

P4-Div

32

P5-Div

4

CLK_IN0

CLK_IN1

27MHz

Crystal

SSC-OFF

Y5

Y4

Y3

Y2

Y1

Y0

27MHz

27MHz

27MHz

27MHz

LV

CMOS

LV

CMOS

LV

CMOS

LV

CMOS

LV

CMOS

LV

CMOS

27MHz

DividerM

27

fout=

finxN

MxP

, i.e.fout=

27MHzx8

(1x8)

=27MHz

(1)

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

NOTE: All outputs are enabled and in non-inverting mode. S0, S1, and SSC comply according the default setting described in

Byte 10 and Byte 25 respectively.

Figure 13. Default Device Setting

The output frequency can be calculated:

Copyright © 2005–2007, Texas Instruments Incorporated

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