CDCE906 datasheet(36/42 Pages) TI

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EVM Board Configuration:

•Y0 (PLL1), Y1 3 state

•CLK_IN: Crystal 27 MHz

•measured Channel: Y0

Measurement:

•Start Condition:ƒ(M = 10, N = 30) = 81 MHz

•Byte 2 write: N = 30 (81 MHz) => N = 110 (297 MHz)

Result:

•60ms to PLL Pull In

•90ms to PLL Phase Lock

20 ms/div

297

t [ms]

Start Condition:

Acknowledge of

N-Divider Byte

Frequency

Response

Curve of Y0

f (MHz)

Power Supply Sequence

Device Behavior during Supply Voltage Drops

Typ3.3V

Typ2.1V

Typ1.7V

VCC

VPUC_ON

VPUC_OFF

GND

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

Figure 34. Snapshot of the PLL Lock-Time

The CDCE906 includes the following three power supply pins: VCC, VCCOUT1, and VCCOUT2. There are no power

supply sequencing requirements, as the three power nodes are separated from each other. So, power can be

supplied in any order to the three nodes.

Also, the part has a power-up circuitry which switches the device on if VCC exceeds 2.1 V (typ) and switches the

device off at VCC < 1.7 V (typ). In power-down mode, all outputs and clock inputs are switched off.

The CDCE906 has a Power-Up-Circuit, which activates the device function at VPUC_ON (typical 2.1 V). At the

same time, the EEPROM information is loaded into the register. This mechanism ensures that there is a

pre-defined default after Power-Up and no need to reprogram the CDCE906 in the application.

In the event of a supply-voltage-drop, the Power-Up-Circuit assures that there is always a defined setup within

the register. Figure 35 shows possible voltage drops with different amplitudes.

Figure 35. Different Voltage Drops on VCC During Operation

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