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CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

Byte 9 to 12: Outputs Switch Matrix (5x6 Switch A) PLL Selection for P-Divider P0-P5

SWAPx2

SWAPx1

SWAPx0

Any Output Px

0

0

0

PLL bypass (input clock)

0

0

1

PLL1

P2, P3, P4, P5

0

1

0

PLL2 non-SSC

P0

0

1

1

1

0

0

PLL3

P1

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Reserved

(1)

Unless customer specific setting.

(2)

PLL2 has a SSC output and non-SSC output. If SSC bypass is selected (see Byte 25, Bit [6:4]), the SSC circuitry of PLL2 is

powered-down and the SSC output is reset to logic low. The non-SSC output of PLL2 is not affected by this mode and can still be used.

Byte 10, Bit [1:0]: Configuration Settings of Input S0/A0/CLK_SEL

S01

S00

Function

If S0 is low, the PLLs and the clock-input stage are going into power-down mode, outputs are in

Yes

0

0

If S0 is low, the PLL and all dividers (M-Div and P-Div) are bypassed and PLL is in power-down,

0

1

all outputs are active (inv. or non-inv.), actual register settings will be maintained, SMBus stays

active; this mode is useful for production test;

1

0

— CLK_SEL is set low selects CLK_IN_IN0

— CLK_SEL is set high selects CLK_IN_IN1

In this mode, the control input S0 is interpreted as address bit A0 of the slave receiver address

1

1

(1)

Unless customer specific setting.

(2)

Power-down mode overwrites 3-state or low-state of S1 setting in Byte 10, Bit [3:2].

(3)

If the clock input (CLK_IN0/CLK_IN1) is selected as crystal input or differential clock input (Byte 11, Bit [7:6]) then this setting is not

relevant.

(4)

To use this pin as Slave Receiver Address Bit A0, an Initialization pattern needs to be sent to CDCE906. When S00/S01 is set to be 1,

the S0 input pin will be interpreted in the next read or write cycle as the Address Bit A0 of the Slave Receiver Address Byte. Note that

right after the Byte 10 (S00/S01) has been written, A0 (via S0-pin) will immediately be active (also when Byte 10 is sent within a block

write sequence). After the Initialization each CDCE906 has its own S0 dependent Slave Receiver Address and can be addressed

accordingly to their new valid address.

Byte 10, Bit [3:2]: Configuration Settings of Input S1/A1

S11

S10

Function

0

0

If S1 is set low, all outputs are switched to a low-state (non-inv.) or high-state (inv.);

Yes

0

1

If S1 is set low, all outputs are switched to a 3-state

1

0

Reserved

In this mode, the control input S1 is interpreted as Address Bit A1 of the Slave Receiver Address

1

1

(1)

Unless customer specific setting.

(2)

To use this pin as Slave Receiver Address Bit A1, an Initialization pattern needs to be sent to CDCE906. When S10/S11 is set to be 1,

the S1 input pin will be interpreted in the next read or write cycle as the Address Bit A1 of the Slave Receiver Address Byte. Note that

right after the Byte 10 (S10/S11) has been written, A1 (via S1-pin) will immediately be active (also when Byte 10 is sent within a block

write sequence). After the Initialization each CDCE906 has its own S1 dependent Slave Receiver Address and can be addressed

accordingly to their new valid address.

CLKSEL

Input Clock

0

CLK_IN0

Yes

1

CLK_IN1

(1)

This bit is not relevant, if crystal input or differential clock input is selected, Byte 11, Bit [7:6].

(2)

Unless customer specific setting.

Copyright © 2005–2007, Texas Instruments Incorporated

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