 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CDCE906 Datasheet(PDF) 5 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
CDCE906 Datasheet(HTML) 5 Page - Texas Instruments |
|
|
5 / 42 page  www.ti.com RECOMMENDED OPERATING CONDITIONS RECOMMENDED CRYSTAL SPECIFICATIONS EEPROM SPECIFICATION TIMING REQUIREMENTS CDCE906 SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Device supply voltage 3 3.3 3.6 V VCCOUT1 (1) Output Y0,Y1 supply voltage 2.3 3.6 V VCCOUT2 (1) Output Y2, Y3, Y4, Y5 supply voltage 2.3 3.6 V VIL Low level input voltage LVCMOS 0.3 VCC V VIH High level input voltage LVCMOS 0.7 VCC V VIthresh Input voltage threshold LVCMOS 0.5 VCC V VI Input voltage range LVCMOS 0 3.6 V |VID| Differential input voltage 0.1 V VIC Common-mode for differential input voltage 0.2 Vcc - 0.6 V IOH / IOL Output current (3.3 V) ±6 mA IOH / IOL Output current (2.5 V) ±4 mA CL Output load LVCMOS 25 pF TA Operating free-air temperature 0 70 °C (1) The minimum output voltage can be down to 1.8 V. See the application note for more information. MIN NOM MAX UNIT fXtal Crystal input frequency range (fundamental mode) 8 27 54 MHz ESR Effective series resistance(1) (2) 15 60 Ω CIN Input capacitance CLK_IN0 and CLK_IN1 3 pF (1) For crystal frequencies above 50 MHz the effective series resistor should not exceed 50 Ω to assure stable start-up condition. (2) Maximum Power Handling (Drive Level) see Figure 16. MIN TYP MAX UNIT EEcyc Programming cycles of EEPROM 100 1000 Cycles EEret Data retention 10 Years over recommended ranges of supply voltage, load, and operating-free air temperature MIN NOM MAX UNIT CLK_IN REQUIREMENTS PLL mode 1 167 fCLK_IN CLK_IN clock input frequency (LVCMOS or Differential) MHz PLL bypass mode 0 167 tr / tf Rise and fall time CLK_IN signal (20% to 80%) 4 ns dutyREF Duty cycle CLK_IN at VCC / 2 40% 60% SMBus TIMING REQUIREMENTS (see Figure 11) fSCLK SCLK frequency 100 kHz th(START) START hold time 4 µs tw(SCLL) SCLK low-pulse duration 4.7 µs tw(SCLH) SCLK high-pulse duration 4 50 µs tsu(START) START setup time 0.6 µs th(SDATA) SDATA hold time 0.3 µs tsu(SDATA) SDATA setup time 0.25 µs tr SCLK / SDATA input rise time 1000 ns tf SCLK / SDATA input fall time 300 ns Copyright © 2005–2007, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): CDCE906 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
