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Output Switching Matrix

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

Table 4. Configuration Setting of Control Inputs

Configuration Bits

External Control Pins

Device Function

Byte 10,

Bit [3:2]

Bit [1:0]

S11

S10

S01

S00

Yx Outputs

Power

Pin 2

Pin 1

(Pin 2)

(Pin 1)

Down

Active

Output ctrl

Low/High(1)

Output ctrl

3-State

Outputs only

Output ctrl

3-State

PLL, inputs and outputs

Output ctrl

Output ctrl and pd

S10=0: low/high(1)

PLL only

Output ctrl

PLL and Div bypass

S10=1: 3-State

Active

PLL only

Output ctrl

PLL and Div bypass

0/1(2)

S10=0: Low/High(1)

Output ctrl

CLK_SEL

S10=1: 3-State

0/1(2)

Active

Output ctrl

CLK_SEL

Active

A1(3)

A0(3)

(1)

A non-inverting output will be set to low and an inverting output will be set to high.

(2)

If S0 is 0, CLK_IN0 is selected; if S0 is 1, CLK_IN1 is selected.

(3)

S0 and S1 are interpreted as Address Bit A0 and A1 of the Slave Receiver Address Byte.

As shown in Table 4, there is a specific order of the different output condition: Power-down mode overwrites

3-state, 3-state overwrites low-state, and low-state overwrites active-state.

The flexible architecture of the output switch matrix allows the user to switch any of the internal clock signal

sources via a free-selectable post-divider to any of the six outputs.

As shown in Figure 24, the CDCE906 is based on two banks of switches and six post-dividers. Switch A

comprises six 5-Input-Muxes which selects one of the four PLL clock outputs or directly selects the input clock

and feed it to one of the 7-bit post-divider (P-Divider). Switch B is made up of six 6-Input-Muxes which takes any

post-divider and feeds it to one of the six outputs, Yx.

Switch B was added to the output switch matrix to ensure that outputs frequencies derive from one P-divider are

100% phase aligned. Also, the P-divider is built in a way that every divide factor is automatically duty-cycle

corrected. Changing the divider value on the fly may cause a glitch on the output.

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