6402 datasheet(108/250 Pages) INTEL

108 / 250 page

Transparent Mode

108

Intel® 6400/6402 Advanced Memory Buffer Datasheet

Note:

1. Ioh: current into a 50-ohm external load to ground, with on-die transmitter

termination enabled

2. Iol: current into a 50-ohm external load to 1.5 V supply rail, with on-die

transmitter termination enabled

10.2.6

IO Implementation Guidelines

10.2.6.1

Dedicated Receivers

Simple one-stage receivers for the transparent mode have been added in parallel to the

existing high-speed sampling receivers. The latter can be turned off during transparent

mode, as well as the DRC and the phase interpolator, to save power and avoid noise.

An internal VREF set to 0.25 V will be used, so the tester signals should oscillate

between 0 and 0.5 V. The transparent mode RX should be turned off during normal

mode, so as to save power/avoid noise.

10.2.6.2

Common Clock Scheme

To avoid costly implementations using strobes and FIFOs, a common clock scheme is

followed, implemented in the core, where the data capture flops reside. Since

transparent mode data signals from the tester are all in phase with the 100 MHz

system clock, the clock used for the capture flops has to be aligned with the external

system clock (or slightly delayed, to account for the propagation delay difference

between data receivers and clock receiver).

Aligning core clock and external clock can be done using the HVM mode circuitry

included in the PLL. The HVM clock tree will have to feed the capture flops, and one of

its leaves has to be fed back to the PLL, in order to achieve adequate synchronization.

10.2.6.3

Tester Interface Clock and Data Routing

The following uncertainties have to be factored in:

• Tester board (TIU) trace mismatches

• Package trace mismatches

• FBD low speed RX propagation delay variations due to PVT

• Set up and hold of capture flops (typically <350 ps depending on process, voltage

and temperature)

• Clock synchronization mismatch, core clock PLL and tree jitter (approximately

±200 pS)

At 200 MHz, there is a 5 ns data window. The potential FBD low speed receiver

variation is approximately 300 ps propagation variation over process, voltage and

temperature. Package and tester interface mismatches are not expected to exceed

Vih (AC)

350

900

Voh

400

Vol

100

Ioh

Iol

Table 10-5. Transparent Mode FB-DIMM Interface Signaling Specifications (Sheet 2 of 2)

Minimum

Maximum

Units

6402 Datasheet(PDF) 108 Page - Intel Corporation

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