6402 datasheet(112/250 Pages) INTEL

112 / 250 page

DDR MemBIST

112

Intel® 6400/6402 Advanced Memory Buffer Datasheet

provides two 72 bit words, or 144 bits of test data for each DRAM clock cycle. The data

is supplied to the DRAMs on “early” and “late” phases of the DDR clock cycle. Early data

is provided on the rising edge of CK. Late data is provided one half cycle later on the

falling edge of CK. DRAM compare data is treated in a similar manner with appropriate

clock alignment.

11.2

MemBIST Feature Summary

Table 11-1 lists the features of MemBIST in summary form. Each feature is explained

in subsequent sections. The registers used to control these features are detailed in the

MemBIST register section.

Table 11-1. MemBIST Feature Summary (Sheet 1 of 2)

Feature

Feature Description

Memory Address Control

Address pattern in tests

User defined start and end physical address

Fast X, Fast Y, Fast XY, XZY address modes

Choice of incrementing or decrementing addresses

Dynamic address inversion (DAI) inverts alternate addresses

X (row) address bits

Up to 16

Y (column) address bits

Up to 13 (limited by MTR:numcol to A[13:11,9:0])

Z (bank) address bits

Up to 3

Data Patterns

Static data patterns

fixed nibble data patterns (0, 3, 5, 6, 9, A, C, F)

144-bit user-defined data pattern

288-bit user-defined data pattern

Dynamic data patterns

32-bit user-defined circular shifted data pattern

Random data pattern derived from user-specified 32-bit seed using

an LFSR (CRC32)

Data pattern inversion

Any data pattern can be inverted before being applied

Programmable DRAM Timing Control

DDR2 DRAM timing

Set in AMB registers

Burst Length

4 or 8

Refresh control

DDR2 refresh intervals programmable in AMB registers

BIST Engine Control

Fundamental commands

Write, read, read with data compare, write + read with data compare

Access method

all registers and settings accessible using FBD, JTAG, or SMBus

DRAM data width

x4 or x8

DRAM initialization and mode settings

Set by AMB registers

Execution speed

A programmable number of deselect commands may be inserted

after DRAM accesses to slow down the speed of execution

Execution control

Halt on error or run to completion of test

Test abort during the test

6402 Datasheet(PDF) 112 Page - Intel Corporation

6402 Datasheet(HTML) 112 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL