6402 datasheet(114/250 Pages) INTEL

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DDR MemBIST

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

In addition, MemBIST has 4 fundamental commands which can be utilized directly by

the user. They are write, read, read with data compare, and write followed by read

with data compare. They are also used by the MemBIST built-in algorithms. Some

MemBIST algorithms also utilize additional fundamental commands that are not

available to users. As a result, users cannot duplicate all algorithm functionality by

sequentially running individual MemBIST commands.

11.3.2

Memory Addressing

A memory test is characterized by a starting address, an ending address and a

direction. The address generation logic has counters for row, column and bank

addresses. MemBIST does not change the rank bit during execution. Each rank on a

DIMM must be tested by a separate execution of MemBIST.

Addresses in MemBIST are logical addresses, meaning they follow the order of the

DRAM external address pins. The actual arrangement of bits in the array (the physical

address) will differ from the logical address. Therefore, an addressing scheme or data

pattern may not be applied to the array exactly as one might think. For example,

accesses to logically adjacent cells will not necessarily access physically adjacent cells.

For general purpose testing such as that intended for MemBIST this is not an issue. In-

depth array testing is best done on a portion of the array where the logical to physical

mapping is known, or in transparent mode where one has full control of address and

data sequencing.

11.3.2.1

Address Definition

All addresses in MemBIST have three components: a row address, a column address

and a bank address. The user communicates these values to MemBIST through 32-bit

registers. Column address 0 is not stored since the DRAMs are 72 bits wide and the

MemBIST engine has an internal 144 bit architecture. Column address 10 is used for

auto-precharge (always low in MemBIST) so it is also not specified in the address

registers.

User-defined start and end addresses are constrained to contain a column address

modulo the burst length. For instance, at BL=4, assume a memory access starts at

column 0. The next access would start at column 4, the next at column 8 and so on

(assuming Fast Y address sequencing). The address register bits reflect these

constraints. BL=4 allows specification of column bits 14..2, while BL=8 allows

specification of column bits 15..3.

Note:

Address register bit 15 “R” = Reserved for future use

Table 11-2. Memory Address Definition, BL=4

Address register bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210

15 14 13 12 11 10 9876543210

R 14 13 12 11 98765432210

Row

Column

Bank

6402 Datasheet(PDF) 114 Page - Intel Corporation

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