6402 datasheet(118/250 Pages) INTEL

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DDR MemBIST

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

underflow is applied to the next, or Z, counter. When counter Z reaches its limit, its

overflow or underflow is applied to counter X. A counter that overflows or underflows

resets to its initial starting value and continues counting from that value.

When using XZY addressing, MemBIST accesses the banks specified by

MB_START_ADDR and MB_END_ADDR (with range addressing) or bank 0 through the

MTR limit (with full addressing).

When using XZY addressing, MemBIST accesses multiple banks.

• With range addressing (MBCSR:atype = 0x2), the banks accessed are in the

inclusive range specified by MB_START_ADDR:ba and MB_END_ADDR:ba.

• With full addressing (MBCSR:atype = 0x3), the bank address is bank 0 through the

MTR limit.

When using Fast X, Fast Y or Fast XY addressing, MemBIST will traverse a single bank.

• With range addressing (MBCSR:atype = 0x2), the bank is specified by

MB_START_ADDR:ba. MB_END_ADDR:ba is ignored.

• With full addressing (MBCSR:atype = 0x3), the bank address is always 0.

The direction of sequencing through the test address space is chosen using the

MBCSR:adir field. In this field, either incrementing addresses or decrementing

addresses may be selected. The beginning and ending addresses for the counters

depend upon the choice of addressing type programmed in MBCSR:atype. With range

addressing, the counter limits are specified in MB_START_ADDR and in

MB_END_ADDR. With full addressing, the counter limits are 0 and the MTR limit for

each counter. Special cases which exist for the bank address are specified in

Table 11-4.

11.3.2.4

Details and Examples

11.3.2.4.1

Fast Y

Figure 11-2 below depicts how Fast Y with incrementing addresses cycles through a

range of addresses specified by MB_START_ADDR and MB_END_ADDR. In this

execution mode, Z, or bank address, is held constant (except in the case of dynamic

address inversion mode, DAI, mentioned later). The order in which the locations are

accessed is shown in the boxes representing the memory locations. Note that the Y (or

column) address counter counts from Ys to Ye before incrementing the X (or row)

address counter and beginning again at Ys. This process continues until both the X and

Y address counters reach their end values simultaneously. This ending condition

results in the address range being covered once. The name “Fast Y” is descriptive of

this testing order in which the Y address range changes faster than the X address

range.

6402 Datasheet(PDF) 118 Page - Intel Corporation