6402 datasheet(113/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

113

DDR MemBIST

11.3

MemBIST Operation

11.3.1

Fundamental Operations

The MemBIST logic provides a number of operational modes which can be combined in

various ways to provide a large number of useful combinations. For example, there is a

mode in which it is possible to select address incrementing first by column and then by

row, or the opposite of this. There is also a mode to dynamically invert every other

address, which toggles all address lines to opposite states. These two independent

modes can be combined to test a bank by toggling row address lines to opposite states

or by toggling column address lines to opposite states. Limits on combinations are

mentioned where they exist.

MemBIST also provides a number of complete operations which it can perform.

MemBIST operations can be characterized as a task which MemBIST carries out

automatically after being programmed for the task. The operation begins when

MBCSR:start is set by the user and ends when MemBIST clears this same bit.

MemBIST operations include built-in algorithms and fundamental commands.

MemBIST built-in algorithms consist of complete testing schemes which are

implemented in MemBIST and which carry out complete tests for meeting specific

testing objectives. They accomplish their testing completely under automatic control

once the operation is started.

Failure data access

Failure data logged and accessible using FBD, JTAG or SMBus

Logging may be delayed to capture later failures

Algorithms Provided

Algorithms operate over a specified address range with a fixed data pattern of 0xA only

Notation for algorithm definitions:

^ = increasing address from start to end

v = decreasing address from end to start

W / R = Write / Read and check

D / I = Data / Inverted Data

number = sequence of events

(x, y) = for each address, first x is applied, then y, before continuing to next address

Scan

^ (WD1); ^(RD2); ^ (WI3); ^ (RI4)

Init

^ (WD1)

Mats+

^(WD1); ^(RD2, WI3); v(RI4, WD5);

MarchC–

^(WD1); ^(RD2, WI3); ^(RI4, WD5);

v(RD6, WI7); v(RI8, WD9); v(RD10);

Read and check

^(RD1);

Error Logging

Error logging

Pass / fail indicator

Log up to 5 failing addresses

Record up to 4 sets of 144-bit failure data

144-bit failure data bit location accumulator marking bit failures

through entire test

Table 11-1. MemBIST Feature Summary (Sheet 2 of 2)

Feature

Feature Description

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