6402 datasheet(140/250 Pages) INTEL

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DDR MemBIST

140

Intel® 6400/6402 Advanced Memory Buffer Datasheet

• In WR_SEED state, MemBIST will create 5 crc32 data sets and load into MBDATA4/

5/6/7/9 from the initial seed register MBLFSRSED. When 5 sets of random data are

loaded into MBDATA, the FSM will transition out of this state to WR_NXTAD state.

• In the WR_NXTAD state, the next address for the operation is calculated and the

address issued. The FSM then transitions to the WR_AVAIL state immediately.

• The FSM will alternate between WR_NXTAD and WR_AVAIL until all writes are

issued. In the WR_AVAIL state, a write command will be issued. Once the previous

cycle’s DRAM timing requirements are met (indicated by cget true), the FSM leaves

the WR_AVAIL state. If the write command issued was not to the last address, the

FSM will transition to WR_NXTAD. If this was the last address, the FSM will go to

WR_WAIT state.

• In the WR_WAIT state, the FSM will wait for the timing for the last write to be met,

and then will transition to the WR_DONE state.

• If this is a write only operation, then the FSM will go back to the IDLE state. If this

is a write with read comparison test, the FSM will go to the RD_START state.

• In RD_START state, FSM will look at the decoding of DATA type selection. If LFSR

data type generation is selected, FSM will go to RD_SEED state. If not, FSM will

directly go to RD_NXTAD state.

• In RD_SEED state, MemBIST will create 5 crc32 data sets and load into MBDATA4/

5/6/7/9 from the initial seed register MBLFSRSED. When 5 sets of random data is

set and loaded into MBDATA, FSM will transit out of this state to RD_NXTAD state.

• In the RD_NXTAD state, the next address for the operation is calculated and the

address issued. The FSM transitions to the RD_AVAIL state immediately.

• The FSM will alternate between RD_NXTAD and RD_AVAIL until all reads are issued.

In the RD_AVAIL state, a read command will be issued. Once the previous cycle’s

DRAM timing requirements are met (indicated by cget true), the FSM leaves the

RD_AVAIL state. If the read command issued was not to the last address, the FSM

will transition to RD_NXTAD. If this was the last address, the FSM will go to

RD_WAIT state. If this is a back to back read/write operation, the FSM will transit

from the RD_AVAIL state to the RD_NXTWR state.

• In the RD_NXTWR state, the address for the write command will be issued (which

is the same as the read address previously used). The FSM then transitions to the

RD_WRAVL state immediately.

• From the RD_WRAVL state, if this is the last address, the FSM will go to the

RD_WAIT state after meeting the DRAM timing requirements. If this is not the last

address, the FSM will go back to the RD_NXTAD state again after meeting the

DRAM timing requirements.

• In the RD_WAIT state, the FSM will wait for the timing requirements for the last

read or write to be met, and then transition to the RD_DONE state.

• From the RD_DONE state the FSM will always go to the IDLE state.

6402 Datasheet(PDF) 140 Page - Intel Corporation

6402 Datasheet(HTML) 140 Page - Intel Corporation

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