6402 datasheet(214/250 Pages) INTEL

214 / 250 page

Registers

214

Intel® 6400/6402 Advanced Memory Buffer Datasheet

14.6.1.11 DRRTC00: Receive Enable Reference Output Timing Control Register

This register determines DQS12, 3, 11, 2, 10, 1, 9, & 0 input buffer enable timing delay

14.6.1.12 DRRTC01: Receive Enable Reference Output Timing Control Register

This register determines DQS16, 7, 15, 6, 14, 5, 13, & 4 input buffer enable timing

delay.

14.6.1.13 DRRTC02: Receive Enable Reference Output Timing Control Register

This register determines DQS17 & 8 input buffer enable timing delay.

14.6.1.14 DQS Calibration Registers

The DQSOFCS is a group of six registers that control the fine delay used to center DQS

edges to the DQ data eye during read operations. There is a delay entry for each nibble

of the DDR data bus for each rank. The coarse delay is controlled by the DRAMDLLC

“Delay Element” and “Delay_Uncomp” are defined in the DRRTC register section. Also

note that there is a separate coarse delay control for each “chunk” of the DDR I/O

cluster as defined in the DRAMDLLC register section.

slvlen_not_at_max[m] = DRAMDLLC.SLVLENm[2:0] < 7; where m is the DDR I/O

cluster chunk number

increment_slvlen[i,n] = slvlen_not_at_max AND ( DQSOFCSi.DQSn[3:0] > 7 ); where i

and n are the DQSOFCS register and DQS field numbers respectively

Device:

NodeID

Function: 4

Offset:

A4h

Bit

Attr

Default

Description

31:24

RWST

20h

RCVEN1203: receiver enable delay for DQS12 and 3

23:16

RWST

20h

RCVEN1102: receiver enable delay for DQS11 and 2

15:8

RWST

20h

RCVEN1001: receiver enable delay for DQS10 and 1

7:0

RWST

20h

RCVEN0900: receiver enable delay for DQS9 and 0

Device:

NodeID

Function: 4

Offset:

A8h

Bit

Attr

Default

Description

31:24

RWST

20h

RCVEN1607: receiver enable delay for DQS16 and 7

23:16

RWST

20h

RCVEN1506: receiver enable delay for DQS15 and 6

15:8

RWST

20h

RCVEN1405: receiver enable delay for DQS14 and 5

7:0

RWST

20h

RCVEN1304: receiver enable delay for DQS13 and 4

Device:

NodeID

Function: 4

Offset:

C4h

Bit

Attr

Default

Description

7:0

RWST

20h

RCVEN1708: receiver enable delay for DQS17 and 8

6402 Datasheet(PDF) 214 Page - Intel Corporation

6402 Datasheet(HTML) 214 Page - Intel Corporation

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