6402 datasheet(210/250 Pages) INTEL

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Registers

210

Intel® 6400/6402 Advanced Memory Buffer Datasheet

14.6.1.4

DDBISTLM: DDR DLL BIST Limits

This register contains test limits for DDR DLL BIST.

14.6.1.5

RCVENAC: Receiver Enable Algorithm Control

This register contains controls for the preamble detection algorithm of the automatic

receiver enable logic. RCVENAC.PWIDTH is used to determine if a “low” pulse in a DQS

waveform is wide enough to be a preamble. RCVENAC.POFFSET is subtracted from the

DCALDATA first edge position result and programmed into the DRRTC registers.

DCALDATA I/O Loopback “All Bits Failed” detail

Bit

Description

Last “First All Bits Failed” Nibble. This bit is set if the nibble associated with this register is one of the

last to capture an entire data burst incorrectly during the test.

reserved

5:0

At the end of the test, this field will contain the minimum DQS delay setting that results all bits of a

burst to be captured incorrectly.

DCALDATA DLL BIST Core Counter detail

Bit

Description

15:0

At the end of the test this two byte register will contain the number of core cycles counted from the

time the associated DLL delay line outputs a “terminal count” number of self-oscillation cycles. The

terminal count is defined by the DDBISTLM.TCOUNT register.

Device:

NodeID

Function: 4

Offset:

90h

Bit

Attr

Default

Description

23:16

RWST

0Fh

TCOUNT: DLL delay line output terminal count

15:0

RWST

000Fh

CVAR: core count variation limit

Device:

NodeID

Function: 4

Offset:

94h

Bit

Attr

Default

Description

23:16

RWST

18h

PWIDTH: Minimum preamble width limit, used to detect if a low

pulse in a DQS waveform is wide enough to be a valid preamble. The

default corresponds to 3/4 of a DRAM clock cycle

15:14

Reserved

13:8

RWST

08h

HWIDTH: Minimum high pulse width limit, used to detect if a high

pulse in a DQS waveform is wide enough to indicate a strobe is

toggling in a valid manner. The default corresponds to 1/4 of a DRAM

clock cycle.

7:6

Reserved

5:0

RWST

10h

POFFSET: Preamble center offset from first rising edge, used to

position the DQS receiver enable relative to the preamble edge

location recorded in the DCALDATA registers. The default value

corresponds to 1/2 of a DRAM clock cycle.

6402 Datasheet(PDF) 210 Page - Intel Corporation

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