6402 datasheet(209/250 Pages) INTEL

209 / 250 page

Intel® 6400/6402 Advanced Memory Buffer Datasheet

209

Registers

First “All Bits Failed” position and Status DQS7

Core Counter DQS7

First “Any Bit Failed” Position and Status DQS7

First “All Bits Failed” position and Status DQS15

Core Counter DQS15

First “Any Bit Failed” Position and Status DQS15

First “All Bits Failed” position and Status DQS6

Core Counter DQS6

First “Any Bit Failed” Position and Status DQS6

First “All Bits Failed” position and Status DQS14

Core Counter DQS14

First “Any Bit Failed” Position and Status DQS14

First “All Bits Failed” position and Status DQS5

Core Counter DQS5

First “Any Bit Failed” Position and Status DQS5

First “All Bits Failed” position and Status DQS13

Core Counter DQS13

First “Any Bit Failed” Position and Status DQS13

First “All Bits Failed” position and Status DQS4

Core Counter DQS4

First “Any Bit Failed” Position and Status DQS4

First “All Bits Failed” position and Status DQS12

Core Counter DQS12

First “Any Bit Failed” Position and Status DQS12

First “All Bits Failed” position and Status DQS3

Core Counter DQS3

First “Any Bit Failed” Position and Status DQS3

First “All Bits Failed” position and Status DQS11

Core Counter DQS11

First “Any Bit Failed” Position and Status DQS11

First “All Bits Failed” position and Status DQS2

Core Counter DQS2

First “Any Bit Failed” Position and Status DQS2

First “All Bits Failed” position and Status DQS10

Core Counter DQS10

First “Any Bit Failed” Position and Status DQS10

First “All Bits Failed” position and Status DQS1

Core Counter DQS1

First “Any Bit Failed” Position and Status DQS1

First “All Bits Failed” position and Status DQS9

Core Counter DQ9

First “Any Bit Failed” Position and Status DQS9

First “All Bits Failed” position and Status DQS0

Core Counter DQS0

First “Any Bit Failed” Position and Status DQS0

Table 14-16. Functional Characteristics of DCALDATA for HVM Algorithms

Byte

I/O Loopback

DLL BIST

DCALDATA I/O Loopback “Any Bit Failed” detail

Bit

Description

First “First Any bit Failed” Nibble. This bit is set if the nibble associated with this register is one of the

first to fail to capture data correctly during the test.

reserved

5:0

At the end of the test, this field will contain the minimum DQS delay setting that results in one or

more bits of a burst to be captured incorrectly.

6402 Datasheet(PDF) 209 Page - Intel Corporation

6402 Datasheet(HTML) 209 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL