6402 datasheet(215/250 Pages) INTEL

215 / 250 page

Intel® 6400/6402 Advanced Memory Buffer Datasheet

215

Registers

slvlen[i,m,n] = DRAMDLLC.SLVLENm[2:0] + increment_slvlen[i,n]

Programable_Delay[i,m,n] = ( Delay Element ) * ( slvlen[i,m,n] + 0.5 +

DQSOFCSi.DQSn[2:0]/8 )

DQS_Delay[i,m,n] = Delay_Uncomp + Programmable_Delay[i,m,n]

Note: these registers may have to be saved and restored on S3

14.6.1.15 DQSOFCS00: DQS Calibration Register

This register determines DQS12, 3, 11, 2, 10, 1, 9, & 0 fine DQS delay when reading

from rank 0.

14.6.1.16 DQSOFCS01: DQS Calibration Register

This register determines DQS16, 7, 15, 6, 14, 5, 13, & 4 fine DQS delay when reading

from rank 0.

Device:

NodeID

Function: 4

Offset:

B4h

Bit

Attr

Default

Description

31:28

RWST

DQS12: Fine delay

27:24

RWST

DQS03: Fine delay

23:20

RWST

DQS11: Fine delay

19:16

RWST

DQS02: Fine delay

15:12

RWST

DQS10: Fine delay

11:8

RWST

DQS01: Fine delay

7:4

RWST

DQS09: Fine delay

3:0

RWST

DQS00: Fine delay

Device:

NodeID

Function: 4

Offset:

B8h

Bit

Attr

Default

Description

31:28

RWST

DQS16: Fine delay

27:24

RWST

DQS07: Fine delay

23:20

RWST

DQS15: Fine delay

19:16

RWST

DQS06: Fine delay

15:12

RWST

DQS14: Fine delay

11:8

RWST

DQS05: Fine delay

7:4

RWST

DQS13: Fine delay

3:0

RWST

DQS04: Fine delay

6402 Datasheet(PDF) 215 Page - Intel Corporation

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