6402 datasheet(219/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

219

Registers

14.6.1.28 DDQSCADP1: DQS DELAY CAL PATTERN 1

This register defines the first 32 bits of the 64 bit long “aggressor” data pattern.

14.6.2

Memory Interface Control

14.6.2.1

DIOMON: DDR I/O Monitor

This register monitors the legsel output of the DDR I/O topcdat chunk and controls the

A/D converter in the DDR I/O used to monitor analog voltage levels.

14.6.2.2

ODTZTC: On-Die Termination Timing Control

This register controls the enable and disable timing of the on-die termination on DQ

and DQS pins. Timing can be adjusted in whole clock increments, or enabled statically.

The ETIMR and DTIMR fields are added in hardware to the SPDPAR13CUR.ODTZ_ETIMR

and SPDPAR13CUR.ODTZ_DTIMR register fields to control termination timing during

reads. The DRRTC register is also used to align the enable/disable time to when read

DQ/DQS signals are expected to arrive at the input pins. The combined default values

of the ODTZTC and SPDPAR13CUR fields enable termination 1/2 DRAM clock cycle

before the leading edge of the read DQS preamble arrives at the DQS pin, and keeps

termination enabled for 5 clock cycles in BL4 mode, and 7 cycles in BL8 mode. The DDR

I/O circuits automatically disable on-die termination when the DQ/DQS pins are

driving. The default register values enable termination during writes at the same time

that the pins are driving, so termination is effectively off during writes.

Device:

NodeID

Function: 4

Offset:

E0h

Bit

Attr

Default

Description

31:0

db339ce1h

ENABLE:

Device:

NodeID

Function: 4

Offset:

F0h

Bit

Attr

Default

Description

ENABLE: Enable A/D converter and update vresult

14:12

RWST

BIASSEL: A/D converter input selection

11:8

RWST

LEGSELOUT: Legsel output of topcdat chunk

7RWST

DIOPWR:

6RV

Reserved

5:0

RWST

00h

VRESULT: A/D converter output

Device:

NodeID

Function: 4

Offset:

F4h

Bit

Attr

Default

Description

RWST

TIMORIDE: timing override. On-Die termination always on during read

operations and when the bus is idle

14:12

RWST

DTIMW: disable time after write data

Reserved

6402 Datasheet(PDF) 219 Page - Intel Corporation

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