6402 datasheet(222/250 Pages) INTEL

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Registers

222

Intel® 6400/6402 Advanced Memory Buffer Datasheet

14.7

DFX Registers (Function 5)

14.7.1

Transparent Mode Registers

14.7.1.1

TRANSCFG: Transparent Mode Configuration

This register enables and controls FBD DFX transparent mode features.

14.7.1.2

TRANDERR[8:0]: Transparent Mode Data Error Logs

This register stores data returned from DRAM byte groups on failing transparent mode

tests.

14.7.1.3

TRANSCTRL: Transparent Mode Control

Device:

NodeID

Function: 5

Offset:

3Ch

Bit

Attr

Default

Description

31:29

Reserved

RWST

ENDOUT: enable data output on transparent data/status pins when

set, output status when clear

RWST

LGFBITS: log bits that fail the compare when set, log raw read data

when clear.

RWST

LGFFAIL: log first failure in any burst position.

25:24

RWST

BSTPOS: burst position to log data/failed bits from when LGFFAIL bit

is not set.

0 = first burst in bl4 or bl8 mode

1 = last burst of bl4, second burst of bl8

2 = third burst of bl8

3 = last burst of bl8

23:20

RWST

DRAMRD: byte of data bus selected to be output on transparent

data/status pins when ENDOUT bit is set.

8= DQS 17 and DQS 8

7= DQS 16 and DQS 7

...

0 = DQS 9 and DQS 0

19:16

RWST

DRAMWR: byte of data bus selected to receive transparent write

data, and byte of data bus to be compared against transparent read

data.

Fh = all bytes

8= DQS 17 and DQS 8

7= DQS 16 and DQS 7

...

0 = DQS 9 and DQS 0

15:0

RWST

0000h

DFTDATA: default data for bytes not selected by the DRAMWR field.

This field has early/even data in the upper 8 bits, and late/odd data

in the lower 8 bits.

Device:

NodeID

Function: 5

Offset:

50h, 4Eh, 4Ch, 4Ah, 48h,46h, 44h, 42h, 40h

Bit

Attr

Default

Description

15:8

RWST

00h

LATE_DATA:

7:0

RWST

00h

EARLY_DATA:

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