6402 datasheet(220/250 Pages) INTEL

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Registers

220

Intel® 6400/6402 Advanced Memory Buffer Datasheet

14.6.2.3

DRAMISCTL: Miscellaneous DRAM DDR Cluster Control

14.6.2.4

DDR2ODTC: DDR2 DRAM On-Die Termination Control

The DDR2ODTC controls the behavior of the ODT output (one ODT output per command

bus copy). There is a separate field to control the behavior for reads to rank0, reads to

rank1, writes to rank0, and writes to rank1. Only the lsb of each field is used, and the

msb has no effect. When an lsb of a field is set to one, the ODT pins will drive high, at

the appropriate time relative to data on the DDR bus, when the selected transaction

(read or write) is issued to the selected rank (0 or 1). If a field is set to 0, the ODT

output continues to drive low during the transaction, as it does during idle cycles.

10:8

RWST

DTIMR: disable time after read data

7:4

RWST

ETIMW: enable time before write data

3:0

RWST

ETIMR: enable time before read data

Device:

NodeID

Function: 4

Offset:

F8h

Bit

Attr

Default

Description

31:13

0000h

Reserved

RWST

VOXSTART: Enable the voltage output crossing control loop in the DDR

I/O. This bit is AND’ed with the SPDPAR1011CUR.vox_start bit.

AVMODE: analog validation mode

OCDLOADENABLE: calibration load placed on incoming signals for DDR2

DRAM OCD calibration

9RW

OCDPOLSEL: set for pull up calibration, clear for pull down

8RW

OCDRCOMPEN:

7:0

RWST

11h

VREFSEL: vref selection

Details of DRAMISCTL VREF Field

Settin

Description

TBD

Device:

NodeID

Function: 4

Offset:

F4h

Bit

Attr

Default

Description

Device:

NodeID

Function: 4

Offset:

FCh

Bit

Attr

Default

Description

7:6

RWST

R1ODTWR: ODT control during writes to CS1

x1: ODT pins will drive high

x0: ODT pins remain driving low

5:4

RWST

R1ODTRD: ODT control during reads to CS1

3:2

RWST

R0ODTWR: ODT control during writes to CS0

6402 Datasheet(PDF) 220 Page - Intel Corporation

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