6402 datasheet(223/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

223

Registers

This register enables and controls FBD DFX transparent mode features.

14.7.2

Logic Analyzer Interface (LAI) Registers

14.7.2.1

LAI: LAI Operation Modes

This register controls and reports the AMB’s LAI mode and Qual controls.

14.7.2.2

SBMATCHU: Upper Southbound Match Register

This register sets the upper 8 bits of data match for three southbound commands.

Device:

NodeID

Function: 5

Offset:

80h

Bit

Attr

Default

Description

7:1

00h

Reserved

0RWST

ENTRNSPMODE: Transparency Mode Enable

1 - Enables Transparency Mod

Device:

NodeID

Function: 5

Offset:

B8h

Bit

Attr

Default

Description

31:16

0000h

Reserved

RWST

RAWMODE: data connected to LAI

0: LAI outputs contain initialization state information prior to L0S then lane

data after L0S

1: LAI outputs connected to FBD data inputs even though valid timing is not

present

Reserved

RWST

QUALMODE:

Assert Qual for all non-filtered frames, or only assert Qual for all non-filtered

frames between start and stop events.

0: Ignore Qual start/stop events

1: Assert Qual after a start event, and deassert Qual after a stop events

RWST

FILTERSYNC:

Filter the frame (do not assert Qual) if the frame is a sync.

0: Disable sync filtering

1: Enable sync filtering

11:6

00h

Reserved

5:0

RWST

3Fh

QUALPERIOD:

Additional number of frames Qual remains asserted

Power-on default to 63

Device:

NodeID

Function: 5

Offset:

BCh

Bit

Attr

Default

Description

31:24

00h

Reserved

23:16

RWST

00h

CMD2:

Upper 8 bits [39:32] of southbound command 2

6402 Datasheet(PDF) 223 Page - Intel Corporation

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