SC28L201 datasheet(25/110 Pages) NXP

25 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

25 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

will enable itself to receive the following data stream. Upon receipt of an address not its

own it would then disable itself. As described below appropriate status bits are available to

describe the operation. Again, for this mode an ‘address byte’ is a byte that has the bit in

the parity position set to logical 1.

The use of the multi-drop mode usually implies a ‘master and slave’ conﬁguration, but is

not required, of the several UART stations so programmed. The software control should

allow time for the slave stations to respond to the receipt of an address bit. Often a reply

from the addressed station is expected to conﬁrm the receipt of the address. Please see

Section 8.2.4 “Mode Register 3 (MR3)”.

Enabling the Wake-up mode: (This mode is variously referred to as ‘9-bit’ or

‘multi-drop’.)

This mode is selected by programming bits MR1[4:3] (the parity bits) to ‘11’. The wake-up

feature has four modes of operation: one strictly under processor control and three

automatic. These modes are controlled by bits 6, 1, 0 in the MR3 register. Bit 6 controls

the loading of the address byte to the RxFIFO and MR3[1:0] determines the sub-mode as

shown in the following list.

MR3[1:0] = 00 Normal Wake-up Mode (default), which is the same as previous UARTs,

and is therefore under full control of the processor. The Host controls operation via

interrupts it receives and commands it writes to the UART Command Registers (CR).

Normal wake-up (the default conﬁguration): The enabling of the Wake-up mode

executes a partial enabling of the receiver state machine. Even though the receiver has

been reset, the Wake-up mode will override the disable and reset condition.

In the default (mode ‘00’ above and the least efﬁcient) conﬁguration for this mode of

operation, a ‘master’ station transmits an address character followed by data characters

for the addressed ‘slave’ station. The slave stations, whose receivers are normally

disabled (not reset), examine the received data stream. Upon recognition of its address bit

(this is the parity bit redeﬁned to indicate the associated byte is an address byte,

not the address itself) interrupts the CPU (by setting RxRDY). The CPU (host) compares

the received address to its station address and enables the receiver if it wishes to receive

the subsequent data characters. Upon receipt of another address character, the CPU may

disable the receiver to initiate the process again.

A transmitted character consists of a start bit; the programmed number of data bits, an

address/data (A/D) bit and the programmed number of stop bits. The CPU selects the

polarity of the transmitted A/D bit by programming bit MR1[2]. MR1[2] = 0 transmits a zero

in the A/D bit position which identiﬁes the corresponding data bits as data. MR1 [2] = 1

transmits a one in the A/D bit position which identiﬁes the corresponding data bits as an

address. The CPU should program the mode register prior to loading the corresponding

data bytes into the TxFIFO.

While in this mode, the receiver continuously looks at the received data stream, whether it

is enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character

into the RxFIFO if the received A/D bit is a one, but discards the received character if the

received A/D bit is a zero. If the receiver is enabled, all received characters are transferred

to the CPU via the RxFIFO. In either case when the address character is recognized the

data bits are loaded into the data FIFO while the A/D bit is loaded into the status FIFO

position normally used for parity error (SR[5]). Framing error, overrun error, and break

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