SC28L201 datasheet(30/110 Pages) NXP

30 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

30 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

7.4.8.3

Interrupt arbitration and IRQN generation

Interrupt arbitration is the process used to determine that an interrupt request should be

presented to the host. The arbitration is carried out between the ‘Interrupt Threshold’ and

the ‘sources’ whose interrupt bidding is enabled by the IMR. The interrupt threshold is part

of the ICR (Interrupt Control Register) and is a value programmed by the user. The

‘sources’ present a value to the interrupt arbiter. That value is derived from four ﬁelds: the

channel number, type of interrupts source, FIFO ﬁll level, and a programmable value. The

interrupt request (IRQN) will be asserted only when one or more of these values exceeds

the threshold value in the interrupt control register will.

Following assertion of the IRQN the host will either assert IACKN (Interrupt Acknowledge)

or will use the command to ‘Update the CIR’. At the time either action is taken the CIR will

capture the value of the source that is prevailing in the arbitration process. (Call this value

the winning bid.)

The SCLK drives the arbitration process. It evaluates the 12 bits of the arbitration bus at

⁄

2 the SCLK rate developing a value for the CIR every two SCLK cycles. New arbitration

values presented to the arbitration block during an arbitration cycle will be evaluated in the

next arbitration cycle.

For sources other than receiver and transmitters the user may set the high order bits of an

interrupt sources bid value, thus tailoring the relative priority of the interrupt sources. The

ﬁll level of their respective FIFOs controls the priority of the receivers and transmitters.

The more ﬁlled spaces in the RxFIFO the higher the bid value; the more empty spaces in

the TxFIFO the higher its priority. Channels whose programmable high order bits are set

will be given interrupt priority higher than those with zeros in their high order bits, thus

allowing increased ﬂexibility. The transmitter and receiver bid values contain the character

counts of the associated FIFOs as high order bits in the bid value. Thus, as a receivers

RxFIFO ﬁlls, it bids with a progressively higher priority for interrupt service. Similarly, as

empty space in a transmitters TxFIFO increases, its interrupt arbitration priority increases.

The programmable ﬁelds allow the software to adjust the authority or value of the bid for

those devices not having a FIFO.

Table 4:

Interrupt values

Type

Bit 11 to bit 4

Bit 3

Bit 2

Bit 1

Bit 0

receiver without error

RxFIFO ﬁlled Byte Count

channel number

receiver with error

RxFIFO ﬁlled Byte Count

channel number

receiver watchdog

RxFIFO ﬁlled Byte Count

channel number

transmitter

TxFIFO empty Byte Count

channel number

change of break

programmed ﬁeld

1110

channel number

Rx loopback error

programmed ﬁeld

1111

channel number

change-of-state

programmed ﬁeld

0110Port 0 or 1

Xon/Xoff

programmed ﬁeld

0111

channel number

Counter/Timer

programmed ﬁeld

1000

Counter 0 or 1

address recognition

programmed ﬁeld

1011

channel number

no interrupt

0000-

threshold

bits 7:0 of Interrupt Control Register (ICR)

00000

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