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SC28L201 Datasheet(PDF) 99 Page - NXP Semiconductors |
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SC28L201 Datasheet(HTML) 99 Page - NXP Semiconductors |
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99 / 110 page  9397 750 13138 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 31 October 2005 99 of 110 Philips Semiconductors SC28L201 3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO DACKN LOW requires two rising edges of X1 clock after CEN is LOW. Fig 10. Bus timing, write cycle (68000 mode) DACKN LOW requires two rising edges of X1 clock after CEN is LOW. Fig 11. Interrupt cycle timing (68000 mode) A0 to A6 tCSC tsu(RWL-CEN)(mot) tsu(An-RWL) td(RWD)(mot) D0 to D7 002aab477 X1/SCLK R/WN CEN th(RWH-CEN) th(RWL-An) DACKN tDCW tDAT th(D)(mot) tsu(D)(mot) IRQN tCSC D0 to D7 tDv(RL) td(D)(float) 002aab478 X1/SCLK IACKN DACKN tDCR tDAT |
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