SC28L201 datasheet(48/110 Pages) NXP

48 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

48 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

8.2.4 Mode Register 3 (MR3)

Table 19:

MR3 - Mode Register 3 (address 0x23) bit description

Bit

Symbol

Description

Xon/Xoff transparency [1]. Xon/Xoff character stripping.

0 = ﬂow control characters received are loaded onto the RxFIFO

1 = ﬂow control characters received are not loaded onto the RxFIFO

Control the handling of recognized Xon/Xoff characters. If set, the character

codes are placed on the RxFIFO along with their status bits just as ordinary

characters are. If the character is not loaded onto the RxFIFO, its received

status will be lost unless the receiver is operating in the block error mode, see

MR1[5] and the general discussion on receiver error handling. Interrupt

processing is not effected by the setting of these bits. See Section 6.1.9

“Character and address recognition”.

Address recognition transparency [1]. Xon/Xoff character stripping.

0 = address characters received are loaded to RxFIFO

1 = address characters are not loaded onto the RxFIFO

Control the handling of recognized Address characters. If set, the character

codes are placed on the RxFIFO along with their status bits just as ordinary

characters are. If the character is not loaded onto the RxFIFO, its received

status will be lost unless the receiver is operating in the block error mode, see

MR1[5] and the general discussion on receiver error handling. Interrupt

processing is not effected by the setting of these bits. See Section 6.1.9

“Character and address recognition”.

5:4

reserved

3:2

In-band ﬂow control mode. Xon/Xoff processing.

00 = host mode; only the host CPU may initiate ﬂow control actions through

the CR.

01 = auto transmitter ﬂow control

10 = auto receiver ﬂow control

11 = auto Rx and Tx ﬂow control

Control the Xon/Xoff processing logic. Auto Transmitter ﬂow control allows the

gating of Transmitter activity by Xon/Xoff characters received by the Channel’s

receiver. Auto Receiver ﬂow control causes the Transmitter to emit an Xoff

character when the RxFIFO has loaded to a depth of 240 characters. Draining

the RxFIFO to a level of 128 or less causes the Transmitter to emit an Xon

character. All transmissions require no host involvement. A setting other than

00 in this ﬁeld precludes the use of the command register to transmit Xon/Xoff

characters.

Remark: Interrupt generation in Xon/Xoff processing is controlled by the IMR

(Interrupt Mask Register) of the individual channels. The interrupt may be

cleared by a read of the XISR, the Xon/Xoff Interrupt Status Register. Receipt

of a ﬂow control character will always generate an interrupt if the IMR is so

programmed. The MR0[3:2] bits have effect on the automatic aspects of ﬂow

control only, not the interrupt generation.

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