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LPC1850 Datasheet(PDF) 151 Page - NXP Semiconductors |
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LPC1850 Datasheet(HTML) 151 Page - NXP Semiconductors |
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151 / 157 page ![]() LPC1850_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Preliminary data sheet Rev. 3 — 6 December 2011 151 of 157 NXP Semiconductors LPC1850/30/20/10 32-bit ARM Cortex-M3 microcontroller LPC1850_30_20_10 v.2.1 20110822 Preliminary data sheet - LPC1850_30_20_10 v.2 Modifications: • LQFP100 pin package added in Table 3. • Number of ADC channels, QEI, and Motor control PWM added in Table 2. • Pin P2_7 designated as ISP entry pin. • Description of ISP mode added (see Section 7.8.1). • Updates related to the Rev ‘A’ version of parts LPC1850/30/20/10: – VI updated for I/O pins in Table 6. – Boot pins corrected in Table 3 and Table 5: Pin P2_7 replaced by pin P2_9 as boot pin. Pin level corrected for 4th boot pin (P2_9) in Table 5. – USART3 boot mode added in Table 5. – Memory map updated: SPIFI data added at address 0x1400 000 in Figure 9. – Boot ROM size increased to 64 kB in Section 2 and Figure 9. • Updated pin P2_2, CTOUT_6 changed to CTIN_6 in Table 3. Table 35. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes |
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