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RM48L930 Datasheet(PDF) 40 Page - Texas Instruments |
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RM48L930 Datasheet(HTML) 40 Page - Texas Instruments |
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40 / 147 page  AddressWaitstates DataWaitstates RAM AddressWaitstates DataWaitstates Flash 0MHz 0MHz 0MHz 0MHz 100MHz 0 1 3 0 0 0 150MHz 2 120MHz 1 200MHz 200MHz 200MHz 200MHz 50MHz RM48L930 RM48L730 RM48L530 SPNS176 – SEPTEMBER 2011 www.ti.com 3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains Table 3-1. Clock Domain Timing Specifications Parameter Description Conditions Min Max Unit fHCLK HCLK - System clock frequency Pipeline mode 200 MHz enabled Pipeline mode 50 MHz disabled fGCLK GCLK - CPU clock frequency fHCLK MHz fVCLK VCLK - Primary peripheral clock 100 MHz frequency fVCLK2 VCLK2 - Secondary peripheral clock 100 MHz frequency fVCLK3 VCLK3 - Secondary peripheral clock 100 MHz frequency fVCLKA1 VCLKA1 - Primary asynchronous 100 MHz peripheral clock frequency fVCLKA3 VCLKA3 - Primary asynchronous 48 peripheral clock frequency fVCLKA4 VCLKA4 - Secondary asynchronous 50 MHz peripheral clock frequency fRTICLK RTICLK - clock frequency fVCLK MHz 3.4 Wait States Required Figure 3-1. Wait States Scheme As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required. The TCM flash can support zero address and data wait states up to a CPU speed of 50MHz in non-pipelined mode. The flash supports a maximum CPU clock speed of 200MHz in pipelined mode with one address wait state and three data wait states. The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait state. 40 Device Operating Conditions Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: RM48L930 RM48L730 RM48L530 |
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