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RM48L930 Datasheet(PDF) 67 Page - Texas Instruments |
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RM48L930 Datasheet(HTML) 67 Page - Texas Instruments |
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67 / 147 page  RM48L930 RM48L730 RM48L530 www.ti.com SPNS176 – SEPTEMBER 2011 Table 4-21. Device Memory Map (continued) FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO FRAME CHIP FRAME ACTUA MODULE NAME UNIMPLEMENTED LOCATIONS IN SELECT SIZE L SIZE START END FRAME MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128KB 2KB Abort for accesses above 2KB Wrap around for accesses to unimplemented address offsets lower DCAN3 RAM PCS[13] 0xFF1A_0000 0xFF1B_FFFF 128KB 2KB than 0x7FF. Abort generated for accesses beyond offset 0x800. Wrap around for accesses to unimplemented address offsets lower DCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128KB 2KB than 0x7FF. Abort generated for accesses beyond offset 0x800. Wrap around for accesses to unimplemented address offsets lower DCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128KB 2KB than 0x7FF. Abort generated for accesses beyond offset 0x800. Wrap around for accesses to unimplemented address offsets lower MIBADC2 RAM PCS[29] 0xFF3A_0000 0xFF3B_FFFF 128KB 8KB than 0x1FFF. Abort generated for accesses beyond 0x1FFF. Wrap around for accesses to unimplemented address offsets lower MIBADC1 RAM PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128KB 8KB than 0x1FFF. Abort generated for accesses beyond 0x1FFF. Wrap around for accesses to unimplemented address offsets lower N2HET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128KB 16KB than 0x3FFF. Abort generated for accesses beyond 0x3FFF. Wrap around for accesses to unimplemented address offsets lower N2HET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB than 0x3FFF. Abort generated for accesses beyond 0x3FFF. N2HET2 TU2 PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128KB 1KB Abort RAM N2HET1 TU1 PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB Abort RAM Debug Components CoreSight Debug Reads return zeros, writes have no CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB ROM effect Cortex-R4F Reads return zeros, writes have no CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Debug effect Reads return zeros, writes have no ETM-R4 CSCS2 0xFFA0_2000 0xFFA0_2FFF 4KB 4KB effect Reads return zeros, writes have no CoreSight TPIU CSCS3 0xFFA0_3000 0xFFA0_3FFF 4KB 4KB effect POM CSCS4 0xFFA0_4000 0xFFA0_4FFF 4KB 4KB Abort Peripheral Control Registers Reads return zeros, writes have no HTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B effect Reads return zeros, writes have no HTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B effect Reads return zeros, writes have no N2HET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B effect Reads return zeros, writes have no N2HET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B effect Reads return zeros, writes have no GIO PS[16] 0xFFF7_BC00 0xFFF7_BCFF 256B 256B effect Reads return zeros, writes have no MIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B effect Copyright © 2011, Texas Instruments Incorporated System Information and Electrical Specifications 67 Submit Documentation Feedback focus.ti.com: RM48L930 RM48L730 RM48L530 |
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