RM48L930 datasheet(69/147 Pages) TI1

69 / 147 page

RM48L930

RM48L730

RM48L530

www.ti.com

SPNS176

– SEPTEMBER 2011

Table 4-21. Device Memory Map (continued)

FRAME ADDRESS RANGE

RESPNSE FOR ACCESS TO

FRAME CHIP

FRAME

ACTUA

MODULE NAME

UNIMPLEMENTED LOCATIONS IN

SELECT

SIZE

L SIZE

START

END

FRAME

Reads return zeros, writes have no

DCC2

PPS5

0xFFFF_F400

0xFFFF_F4FF

256B

effect

Reads return zeros, writes have no

ESM

PPS5

0xFFFF_F500

0xFFFF_F5FF

256B

effect

Reads return zeros, writes have no

CCMR4

PPS5

0xFFFF_F600

0xFFFF_F6FF

256B

effect

Reads return zeros, writes have no

DMM

PPS5

0xFFFF_F700

0xFFFF_F7FF

256B

effect

Reads return zeros, writes have no

RAM ECC even

PPS6

0xFFFF_F800

0xFFFF_F8FF

256B

effect

Reads return zeros, writes have no

RAM ECC odd

PPS6

0xFFFF_F900

0xFFFF_F9FF

256B

effect

Reads return zeros, writes have no

RTP

PPS6

0xFFFF_FA00

0xFFFF_FAFF

256B

effect

Reads return zeros, writes have no

RTI + DWWD

PPS7

0xFFFF_FC00

0xFFFF_FCFF

256B

effect

Reads return zeros, writes have no

VIM Parity

PPS7

0xFFFF_FD00

0xFFFF_FDFF

256B

effect

Reads return zeros, writes have no

VIM

PPS7

0xFFFF_FE00

0xFFFF_FEFF

256B

effect

System Module -

Reads return zeros, writes have no

Frame 1 (see

PPS7

0xFFFF_FF00

0xFFFF_FFFF

256B

effect

device TRM)

System Information and Electrical Specifications

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