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RM48L930 Datasheet(PDF) 97 Page - Texas Instruments |
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RM48L930 Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 147 page  RM48L930 RM48L730 RM48L530 www.ti.com SPNS176 – SEPTEMBER 2011 4.19 Reset / Abort / Error Sources Table 4-36. Reset/Abort/Error Sources ESM HOOKUP ERROR SOURCE SYSTEM MODE ERROR RESPONSE group.channel CPU TRANSACTIONS Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) n/a Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) n/a Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) n/a Undefined Instruction Trap Illegal instruction User/Privilege n/a (CPU)(1) MPU access violation User/Privilege Abort (CPU) n/a SRAM B0 TCM (even) ECC single error (correctable) User/Privilege ESM 1.26 Abort (CPU), ESM = > B0 TCM (even) ECC double error (non-correctable) User/Privilege 3.3 nERROR B0 TCM (even) uncorrectable error (i.e. redundant address User/Privilege ESM = > NMI 2.6 decode) B0 TCM (even) address bus parity error User/Privilege ESM = > NMI 2.10 B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28 Abort (CPU), ESM = > B1 TCM (odd) ECC double error (non-correctable) User/Privilege 3.5 nERROR B1 TCM (odd) uncorrectable error (i.e. redundant address User/Privilege ESM = > NMI 2.8 decode) B1 TCM (odd) address bus parity error User/Privilege ESM = > NMI 2.12 FLASH FMC correctable error - Bus1 and Bus2 interfaces User/Privilege ESM 1.6 FMC uncorrectable error - Bus1 accesses Abort (CPU), ESM = > User/Privilege 3.7 (does not include address parity error) nERROR FMC uncorrectable error - Bus2 accesses (does not include address parity error and EEPROM bank User/Privilege ESM = > nERROR 3.7 accesses) FMC uncorrectable error - address parity error on Bus1 User/Privilege ESM = > NMI 2.4 accesses FMC correctable error - Accesses to EEPROM bank User/Privilege ESM 1.35 FMC uncorrectable error - Accesses to EEPROM bank User/Privilege ESM 1.36 DMA TRANSACTIONS External imprecise error on read (Illegal transaction with ok User/Privilege ESM 1.5 response) External imprecise error on write (Illegal transaction with ok User/Privilege ESM 1.13 response) Memory access permission violation User/Privilege ESM 1.2 Memory parity error User/Privilege ESM 1.3 DMM TRANSACTIONS External imprecise error on read (Illegal transaction with ok User/Privilege ESM 1.5 response) External imprecise error on write (Illegal transaction with ok User/Privilege ESM 1.13 response) HET TU (HTU) NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt = > VIM n/a External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt = > VIM n/a Memory access permission violation User/Privilege ESM 1.9 (1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of the CPU. Copyright © 2011, Texas Instruments Incorporated System Information and Electrical Specifications 97 Submit Documentation Feedback focus.ti.com: RM48L930 RM48L730 RM48L530 |
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