RM48L930 datasheet(82/147 Pages) TI1

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EMIF_CLK

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

BASIC SDRAM

WRITE OPERATION

EMIF_CS[0]

EMIF_DQM[1:0]

EMIF_nRAS

EMIF_nCAS

EMIF_nWE

RM48L930

RM48L730

RM48L530

SPNS176

– SEPTEMBER 2011

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4.14.2.4 Write Timing (Synchronous RAM)

Figure 4-16. Basic SDRAM Write Operation

4.14.2.5 EMIF Asynchronous Memory Timing

Table 4-27. EMIF Asynchronous Memory Timing Requirements

NO.

Value

Unit

MIN

NOM

MAX

Reads and Writes

tw(EM_WAIT)

Pulse duration, EMIFnWAIT

assertion and deassertion

Reads

tsu(EMDV-EMOEH)

Setup time, EMIFDATA[15:0]

valid before EMIFnOE high

th(EMOEH-EMDIV)

Hold time, EMIFDATA[15:0]

0.5

valid after EMIFnOE high

tsu(EMOEL-EMWAIT)

Setup Time, EMIFnWAIT

4E+3

asserted before end of Strobe

Phase(1)

Writes

tsu(EMWEL-EMWAIT)

Setup Time, EMIFnWAIT

4E+3

asserted before end of Strobe

Phase(1)

(1)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended

wait states. Figure Figure 4-12 and Figure Figure 4-14 describe EMIF transactions that include extended wait states inserted during the

STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start

of where the HOLD phase would begin if there were no extended wait cycles.

System Information and Electrical Specifications

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