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RM48L930 Datasheet(PDF) 122 Page - Texas Instruments

Part # RM48L930
Description  RM48Lx30 16/32-Bit RISC Flash Microcontroller
PDF  147 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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RM48L930 Datasheet(HTML) 122 Page - Texas Instruments

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NHET1
NHET2
NHET_LOOP_SYNC
EXT_LOOP_SYNC
EXT_LOOP_SYNC
NHET_LOOP_SYNC
RM48L930
RM48L730
RM48L530
SPNS176
– SEPTEMBER 2011
www.ti.com
Table 5-9. Dynamic Characteristics for the N2HET Input Capture Functionality
PARAMETER
MIN(1) (2)
MAX(1) (2)
UNIT
1
Input signal period, PCNT or WCAP for rising edge
2 (hr) (lr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
to rising edge
2
Input signal period, PCNT or WCAP for falling edge
2 (hr) (lr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
to falling edge
3
Input signal high phase, PCNT or WCAP for rising
(hr) (lr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
edge to falling edge
4
Input signal low phase, PCNT or WCAP for falling
(hr) (lr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
edge to rising edge
(1)
hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).
(2)
lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR)
Both N2HET1 and N2HET2 have three channels each that are enhanced to be able to capture inputs with
smaller pulse widths than that specified in Table 5-9. These are N2HET1 channels 15, 20 and 31, and
N2HET2 channels 12, 14 and 16.
The input capture capability for these channels is specified in the following table.
Table 5-10. Input Capture Capability for N2HET Channels with Enhancements
PARAMETER
MIN
MAX
UNIT
1
Input signal period, PCNT or WCAP for rising edge
(hr) (lr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
to rising edge
2
Input signal period, PCNT or WCAP for falling edge
(hr) (lr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
to falling edge
3
Input signal high phase, PCNT or WCAP for rising
2 (hr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
edge to falling edge
4
Input signal low phase, PCNT or WCAP for falling
2 (hr) tc(VCLK2) + 2
225 (hr) (lr) tc(VCLK2) - 2
ns
edge to rising edge
5.4.4
N2HET1-N2HET2 Interconnections
In some applications the N2HET resolutions must be synchronized. Some other applications require a
single time base to be used for all PWM outputs and input timing captures.
The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures
the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal
to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to
the loop resolution signal sent by the master. The slave does not require this signal after it receives the
first synchronization signal. However, anytime the slave receives the re-synchronization signal from the
master, the slave must synchronize itself again..
Figure 5-6. N2HET1
– N2HET2 Synchronization Hookup
5.4.5
N2HET Checking
5.4.5.1
Internal Monitoring
To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be
used to monitor each other
’s signals as shown in Figure 5-7. The direction of the monitoring is controlled
by the I/O multiplexing control module.
122
Peripheral Information and Electrical Specifications
Copyright
© 2011, Texas Instruments Incorporated
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