RM48L930 datasheet(141/147 Pages) TI1

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RM48L930

RM48L730

RM48L530

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SPNS176

– SEPTEMBER 2011

Table 5-22. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =

input, and SPISOMI = output)(1)(2)(3)(4)

NO.

Parameter

MIN

MAX

Unit

tc(SPC)S

Cycle time, SPICLK(5)

256tc(VCLK)

2(6)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 1)

3(6)

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 0)

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 1)

4(6)

td(SOMI-SPCL)S

Dealy time, SPISOMI data valid after SPICLK low

trf(SOMI) + 18

(clock polarity = 0)

td(SOMI-SPCH)S

Delay time, SPISOMI data valid after SPICLK high

trf(SOMI) + 18

(clock polarity = 1)

5(6)

th(SPCL-SOMI)S

Hold time, SPISOMI data valid after SPICLK high

(clock polarity =0)

th(SPCH-SOMI)S

Hold time, SPISOMI data valid after SPICLK low (clock

polarity =1)

6(6)

tsu(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high (clock

polarity = 0)

tsu(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low (clock polarity

= 1)

7(6)

tv(SPCH-SIMO)S

High time, SPISIMO data valid after SPICLK high

(clock polarity = 0)

tv(SPCL-SIMO)S

High time, SPISIMO data valid after SPICLK low (clock

polarity = 1)

td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high

1.5tc(VCLK)

2.5tc(VCLK)+tr(ENAn)

(clock polarity = 0)

td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock

1.5tc(VCLK)

2.5tc(VCLK)+tr(ENAn)

polarity = 1)

td(SCSL-SENAL)S

Delay time, SPIENAn low after SPICSn low (if new data

tf(ENAn)

tc(VCLK)+tf(ENAn)+14

has been written to the SPI buffer)

td(SCSL-SOMI)S

Delay time, SOMI valid after SPICSn low (if new data

tc(VCLK)

2tc(VCLK)+trf(SOMI)+8

has been written to the SPI buffer)

(1)

The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2)

If the SPI is in slave mode, the following must be true: tc(SPC)S

≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3)

For rise and fall timings, see the

"switching characteristics for output timings versus load capacitance" table.

(4)

tc(VCLK) = interface clock cycle time = 1 /f(VCLK)

(5)

When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.

(6)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Peripheral Information and Electrical Specifications

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